U.S. Philips Corporation

Laurens Doornhein

Jeroen M Kettenis

Marcellinus J Annegarn

Antonius H Nillesen

Cornelis M Huizer

Johannes G Raven

Petrus W Welles

A television signal includes a video signal having at least luminance information and a signalling bit stream for conveying static control information bits relating e.g. to at least an aspect ratio of the video signal, in which a plurality of bits of an additional data signal are distributed over at least one bit of the signalling bit stream per frame of the video signal, whereby the signalling bit stream contains at least one varying bit in addition to the static control information bits.

Television signal comprising additional data

An integrated circuit comprises a time-discrete oscillator which generates numerical and time-discrete phase values of an oscillator signal. The circuit also comprises a time-continuous oscillator which generates a time-continuous oscillation signal. The circuit comprises a phasemeter which is coupled to the time-continuous oscillator in order to sample phase values of the time-continuous signal. The difference between the generated phase values and the sampled phase values is measured in a comparator circuit. This difference is utilized in a phase-locked loop in order to readjust the frequency of the time-continuous oscillator, so that the time-continuous oscillation is latched to the time-discrete oscillation. The phase comparison can thus be executed in a substantially time-discrete manner. As a result, the operational reproducibility of the circuit is very high. Because phase comparison is not restricted to a single, fixed phase point during the oscillation period, the phase locking exhibits hardly any jitter.

Digital phase-locked loop

An image is sampled at a given sampling frequency. For each original sample at least one additional sample delayed relative to the first sample is generated (12, 14, 16). The original samples are non-linearly processed (18) and the additional samples are non-linearly processed (20) independently of the processing (18) of the original samples. The output signals from the two processing stages are downsampled (22) back to the original sampling frequency and are metered if required for correcting the overall amplitude and phase vs. frequency characteristic.

Non-linear signal processor

A signal transient improvement device includes a delay circuit (1-13) receiving an input signal (C) and having an output supplying an output signal which is a version of the input signal either delayed by a predetermined amount (T3), or delayed by a controllable amount less than or equal to the predetermined amount, and a control circuit (15-23) for controlling the delay circuit. The control circuit calculates the second derivative of the input signal to obtain a control signal, the sign of which indicates whether the input signal is to be delayed by the predetermined amount, or delayed by a controllable amount less than or greater than the predetermined amount, while the amplitude of the control signal indicates the magnitude of the controllable amount less than or greater than the predetermined amount by which the input signal is to be delayed.

Signal transient improvement device having a delay circuit in which the

A serial memory in which serial address input devices share a terminal with control signal input devices is suitable for the non-shifting storage of information and includes at least one address counter which receives address incrementation signals from a clock and which is suitable for receiving a preset address on the serial address input means.

Serial memory with address counter which can be preset using a

In a field number conversion circuit, the mutual positions of the horizontal and vertical synchronizing signal pattern in a field of the television signal to be converted are measured by means of a measuring circuit (201) and these mutual positions are adequately transferred by means of a coupling circuit (203) to a corresponding field in the converted television signal. Reading the field memories (125, 127) used during the conversion operation is preferably effected at a clock frequency (at 53) which is not coupled to the clock frequency (at 23) used during the writing operation.

Field number conversion circuit

In a color television picture display device having an arrangement (47) for converting the number of fields, additional signal paths need not be provided in the arrangement for converting the number of fields, for also displaying a signal combination of high picture quality, such as, for example, a teletext signal combination, with a converted number of fields, if the transmission takes place via the arrangement for converting the number of fields, in a part of the digital signal path combination (63,97; 65,99; 67,101) for the luminance signal, for which purpose a first change-over switch (69) and a second change-over switch (111) are provided at the correct areas.

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Eindhoven, Netherlands

Laurens Doornhein