Unisys Corporation

Burroughs, Inc.

Unisys Corporation (formerly Burroughs Corp.)

Nisys Corporation

Laurence P Flora

Michael A McCullough

David Edgar Castle

Gary V Ruby

Daniel P Wiener

Duane J McCrory

Joseph S Schibinger

LuVerne R Peterson

Greggory D Donley

Manoj Gujral

Craig R Church

Brian Joseph Sassone

A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states

An integrated circuit chip having improved on-chip circuitry including a phase-locked-loop for providing accurately timed signal having different durations and differently occurring timing edges.

IC chip using a phase-locked loop for providing signals having different

A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive. By identifying a data word in a low level cache memory as shared, even when that data word is not in any other low level cache memory, the high level cache memories are able to prevent two computers on separate processor busses from modifying that data word differently; and in addition, the high level cache memories are able to track the data words which get modified.

Method and circuitry for modifying data words in a multi-level

A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between the microprocessor and Network Interface Unit. The Network Interface Unit is memory mapped into the microprocessor's address space. Two memory mapped cache lines are used to write commands to the Network Interface Unit's Write Window and another two cache lines are used to read results of the commands from the Network Interface Unit's Read Window. The Write Window is a three port register file. Data is written into one write port and read simultaneously from two read ports. One read port is used during read operations to the Write Window while the other is used during command execution to move data to the Internal Structures block. The Read Window is a 2-1 multiplexor that is 128 bits wide. On a read operation data may be selected from the Write Window or the Internal Structures.

Low latency message processor interface using memory mapped Read/Write

High speed instruction execution apparatus is disclosed which provides multistage pipelining and branch prediction in a manner which permits speculative changes of state to be made during execution of a predicted instruction before the correctness of the prediction has been determined.

Pipelined microinstruction apparatus and methods with branch prediction

An IC chip employs a common multiplexor logic element in different logic configurations for performing a variety of different logic functions, whereby path delays can be accurately matched. In addition, a phase-locked-loop is employed for providing accurately timed signals having different durations and differently occurring timing edges.

IC chip using a common multiplexor logic element for performing logic

A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full and half adders. This reduction continues until a final set of inputs is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder and a carry lookahead adder to produce the desired product. The additions at each level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder and carry lookahead adder are chosen to further enhance speed while reducing required chip area. A still further enhancement in multiplier operating speed is achieved by providing connections to adders so as to take advantage of the different times of arrival of the inputs to each level along with different adder input-to-output delays.

Enhanced fast multiplier

An integrated circuit chip on which a relatively large on-chip delay is provided using a relatively small delay in conjunction with a phase-locked-loop, whereby the relatively large variations typical of large on-chip delays are avoided.

Methods and apparatus for providing a negative delay on an IC chip

A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full and half adders. This reduction continues until a final set of inputs is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder and a carry lookahead adder to produce the desired product. The additions at each level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder and carry lookahead adder are chosen to further enhance speed while reducing required chip area.

Fast multiplier

A digital adder module has a carry-in terminal, N pairs of data terminals, N sum terminals, and a carry-out terminal. A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel plus one transistor drain plus one internal logic gate plus interconnections between them.

Digital adder having a high-speed low-capacitance carry bypass signal

A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations. An output logical selection circuit merges the selection logic for selecting the correct conditional sum (in response to the look-ahead carry produced) with the conditional subtraction logic required for BCD operation in a manner so that the two operations are performed concurrently during BCD operations.

Fast BCD/binary adder

A multiplicity of independently operating disk drive subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk drive subsystems via the error circuitry such that the overall system appears as a large, high capacity disk drive system having an unusually high fault tolerance and a very high bandpass. Caching is additionally provided in the read/write interface in a manner which takes advantage of the organization provided by the data organizer to significantly improve overall performance. Advantage is also taken of the conventionally provided error detection capability of each disk drive subsystem to enhance the capability of the error circuitry.

High capacity multiple-disk storage method and apparatus having

An execute module in a data processing system is provided with a randomly accessible scratchpad memory which is logically divided into two switchable pages. During operation one page can be written with new instruction data from a fetch module while a previously written page is concurrently being read by the execute module for execution of a designated data processing operation. When the execute module completes execution and requires a new block of data, the two pages are logically switched by toggling an address bit.

Data processing system employing a plurality of rapidly switchable pages

Apparatus for providing automatic clock de-skewing for a plurality of circuit boards of a data processing system. In a preferred embodiment, each circuit board is of multi-layer construction and contains a clock distribution chip which includes on-chip automatic clock de-skewing circuitry for providing de-skewed clocks to other chips on the circuit board. In a preferred implementation of the clock de-skewing circuitry, feedback circuitry including a multi-tapped delay line and an accurate reference delay are employed in conjunction with a phase comparator for automatically providing de-skewed clocks at the clock outputs of the clock distribution chip. The accurate reference delay is advantageously provided by a strip transmission line formed in a conductive layer of the multi-layer board containing the chips.

Automatic clock de-skewing apparatus

A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.

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Covina, CA, United States of America

Laurence P Flora