Agere Systems Guardian Corp.

Lucent Technologies Inc.

Agere Systems Inc.

At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Laurence Edward Bays

Jalil Fadavi-Ardekani

Richard Muscavage

Walter G Soto

Xingdong Dai

Steven R Norsworthy

Dennis A Brooks

Thomas Baker

Bahram Ghaffarzadeh Kermani

Tony S El-Kik

Kenneth Daniel Fitch

Srinivasa Gutta

Richard J Niescier

Richard Niescier

Geoffrey Lawrence Smith

Daniel K Greenwood

Walter P Hays, Iii

Eric Wilcox

A method and apparatus implementing an enhanced protocol between an I2C master and an I2C slave. In various embodiments the invention permits greater addressability space and high priority access to the slave device. The enhanced protocol is implemented by the addition of command code data being transmitted which is recognized through an interface circuit inside the slave device. The invention provides an I2C solution for accessing high priority address space with one command byte, medium priority space with two command bytes and low priority space with three command bytes.

Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput

A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.

Dynamic partitioning of memory banks among multiple agents

A fully-static dual-voltage sense circuit designed for a mixed-voltage system senses the power-rail voltage of other devices that the device is interfaced with, and achieves a low-power consumption level without software assistance when the sensing circuit is active, and protects low-voltage process devices in the circuit from possible high voltage damage at the interface. In a preferred embodiment, the present invention includes an integrated circuit having a dual-voltage sense circuit, the sense circuit including a sense circuit input node supplied with an input voltage Vin; a sense circuit power input node supplied with a power-supply voltage; and a sense circuit output node outputting a digital signal of a voltage level equal to or less than the voltage level of a low-voltage digital signal, regardless of the voltage level of the input voltage.

Low power dual-voltage sense circuit buffer

A computer peripheral device suitable for operation with a Peripheral Component Interconnect (PCI) Bus or the like, has the ability to &ldquo;wakeup&rdquo; the bus from a cold state (e.g., D3,) without the need to supply auxiliary power (e.g., 3.3 volts) to the entire device during the cold state. A modem in the preferred embodiment (although the invention is applicable to other peripheral devices), the device latches device status information from the main circuitry of the device (operating on 5 volts, for example) into a &ldquo;keep alive&rdquo; circuit connected to the auxiliary power supply upon the falling edge of a PCI reset signal (RST&num;). Additionally, the auxiliary power supply also powers a ring detect circuit for the detection of an incoming telephone call, which incoming call triggers a Power Management Event (PME&num;) signal for changing the state of the bus to an active state. Further, the auxiliary power supply powers a RST&num; detection circuit for indicating that a change in the power state of the bus is imminent.

Computer peripheral device having the capability to wake up from a cold state with information stored before cold powerdown

An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.

Processor powerdown operation using intermittent bursts of instruction clock

A new modem architecture that substantially minimizes the cost of adding features to the modem, and substantially minimizes the time overhead associated with the slave-like interface between the modem controller and the modem signal processor. The architecture enables the signal processor to directly access the controller's memory resources so that the signal processor can make most efficient use of its own internal expensive high-speed memory.

Modem architecture for integrated controller and data pump applications

A data converter for converting a signal either from analog form to digital form or from digital form to analog form includes a storage register. The storage register receives and temporarily stores digital data samples. The digital data samples are transferable out of the storage register in the same sequence in which they were received. A digital signal processor coupled to the storage register is interruptible to transferred digital data samples either to or from the storage register. In this manner, the digital signal processor transfers multiple digital data samples either to or from the storage register during each interrupt rather than transferring a single data sample per interrupt, thereby reducing the number of interrupts necessary to transfer a given number of digital data samples.

Data converter with FIFO

A clock generator is described for generating an output clock frequency from an input clock frequency where the frequencies of the clocks are not integrally related. The division process is designed using the quotients of the Euclidean theorem for determining the greatest common divisor of two integers in such a way as to alleviate the adverse effects of jitter. Applications to oversampled sigma-delta codecs are described.

Clock generators having programmable fractional frequency division

A data bus having a given size (e.g., 32 bits) provides for transfer of information between various logic and memory elements within, or among, one or more integrated circuits. Certain of the information transfers require the full information path, while others use only a portion (e.g., 8 or 16 bit transfers). To expedite the transfers of the smaller size words, a given word is replicated to fill up the full data base. This avoids the necessity of specifying the exact location of the smaller word on the data bus.

Growing community of inventors

Allentown, PA, United States of America

Laurence Edward Bays