Unisys Corporation

Laurence D Sawyer

Patrick J Smith

Robert A Lindsay

Steven C Tate

Scott R Bullock

Daniel M Griffin

A novel high speed unidirectional bus system is provided for receiving a plurality of novel circuit card assemblies in receptacles on the bus. Adjacent receptacles are connected by lines on the bus which interconnect output pins to input pins. The circuit between output pins and input pins are formed by connecting the plugs on circuit card assemblies into the receptacles on said bus. The system comprises a plurality of function circuit card assemblies connected in a daisy chain when inserted into adjacent receptacles on said bus between a source circuit card assembly and a destination circuit card assembly and the address portion of the information supplied by the source circuit card assembly is programmed to identify the function circuit card assembly to first receive the source data whereby the unidirectional bus system may be operated in a time division random access mode at data rates in excess of the data rates of individual functional circuit card assemblies.

System for providing a time division random access including a high

An improved interface unit for receiving a stream of parallel bit words from a source bus comprising an address field, a data field and a clock field. The parallel bit words are first phase adjusted and stored in an input register where the address field is compared in enable logic to determine whether to store the data field in a sink buffer register for processing. The word in the input register is coupled to the buffer storage register. The address field is further compared in pass through disable logic to determine whether to pass the address and data field to an output register or to generate a null code address in the address field of the word being outputted from the buffer storage register. The word in the buffer storage register is coupled through a word selector to an output register. A host source is also coupled to the word selector so that a source word may be written into the output register when a null code address is appended to a parallel bit word being supplied as an input to said word selector.

Station interface unit

An I-Q channel adaptive line enhancer has bandpass filters with passbands that can be widened to well beyond the band that is actually being processed by the adaptive line enhancer. This eliminates the requirement of filtering one of the sidebands as is required in single channel adaptive line enhancers, in which the sum and difference sidebands are generated on up-conversion. Band limiting is done with lowpass filters, and the local oscillator may be made variable so that any part of the band that is passed by the bandpass filters can be processed by a single I-Q channel adaptive line enhancer. This type of I-Q channel adaptive line enhancer can process any one of a large number of possible bands without tunable bandpass filters, or without banks of adaptive line enhancers which have been preset to adjacent sub-bands.

I-Q channel adaptive line enhancer

The weights of least mean square (LMS) adaptive filter are updated with a different set of taps than are used to form the output of the adaptive filter in the adaptive processing device of the present invention. As a result of performing the multiplications and sums required for the filter operation simultaneously, an integral number of clock cycle delays appear in the narrowband and error feedback channels. The number of taps of the tapped delay line of the invention are increased, whereby the increased delay through the delay line may be used to compensate for a delay through the filter of an integral number of clock delay cycles. Instantaneous weight updating in accordance with the signal being utilized, may then be achieved at a clock rate frequency that is ten times or more greater than prior art adaptive filters.

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Park City, UT, United States of America

Laurence D Sawyer