Xilinx, Inc.

Lauren B Wenzl

Prasanna Sundararajan

David W Bennett

Jeffrey M Mason

Robert Gwilym Dimond

Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.

Generation of cache architecture from a high-level language description

An interface for an electronic device being coupled to an external device is provided. The interface includes a configurable hardware interface and a storage component for storing a bitstream that configures the configurable hardware interface to implement the driver of the external device. Specifically, the storage component can store one or more bitstreams that correspond to known drivers that can operate with the electronic device. The configurable hardware interface can include a programmable logic device (PLD), a memory, a control interface for controlling the PLD and the memory, and a synchronous communication interface for receiving information from the external device and enabling the control interface. The memory can list the device drivers (i.e. bitstreams) stored in the storage component and their respective addresses. The interface provides the advantage of storing any number of drivers in the device, thereby significantly reducing the time for the two devices to establish communication.

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Niwot, CO, United States of America

Lauren B Wenzl