Vlsi Technology, Inc.

Agilent Technologies, Inc.

Marvell International Technology Ltd

Agilnet Technologies, Inc.

Laura Elisabeth Simmons

Joseph Alan Thomsen

Jonathan Neal Andrews

Stephen Vance Cooper

Marty L Long

David R Evoy

Gregory Frank Carlson

James Daren Bledsoe

Todd Alan McClelland

Gary D Hicok

Patrick Alan McKinley

Franklyn H Story

Scott E Harrow

Paul Chenard

Richard W Ulmer

Rajeev Jayavant

James Ward

Ignacio Jose Perez

Thomas Page Bruch

Salvador Salcido, Jr

Raymond Jensen Hasler

Daniel I Croft

Shelly Rose Reasoner

Chancellor Archie

Charles F McCord, Jr

A service station for a pen that incldues a treadmill belt that has an outer surface and an inner surface and a pen cap positioned on the outer surface of the treadmill belt, wherein the pen cap is positioend between the treadmill belt and the pen. THe service statin further including two rollers upon which the treadmill belt is mounted, wherein the two rollers contact the inner surface of the treatmill belt for driving the treadmill belt. In addition, there is no device positioned between the two rolelrs that engages the inner surface of the treadmill belt so as to move the outer surface toward the pen. THe service statino further includes a drive axle coupled to one of the rollers and a mechanism for switching a direction of travel of the treadmill belt.

Method and system of capping that employs a treadmill belt

The present invention is an integrated system on a chip that combines wireless, graphics, and multimedia. The graphics and multimedia features may be programmed by the end user while restricting programmability of the wireless features.

Integrated circuit architecture for programmable wireless device

An application specific integrated circuit (ASIC) architecture for memory access. A first functional block provides a first address, a first column address strobe signal, and a first read/write signal associated with a first memory access. A second functional block provides a second address, a second column address strobe signal, and a second read/write signal associated with a second memory access. The ASIC architecture includes an embedded memory interface that is coupled to the first functional block and the second functional block. The embedded memory interface provides the first functional block and the second functional block access to an embedded memory either at the same time (referred to herein as concurrent access or simultaneous access) or at different times (referred to herein as consecutive or non-concurrent access). When predetermined conditions are met, the embedded memory interface provides the first functional block and the second functional block concurrent access to the embedded memory. When the predetermined conditions are not met, the embedded memory interface provides consecutive access to the embedded memory.

Embedded memory access method and system for application specific integrated circuits

A printer pen carriage support for a printer is disclosed. The printer pen carriage support includes a cantilever that fits within a groove of a pen carriage and provides support for the pen carriage. Support structures, such as bushings or bearings, may be included to assist in pen carriage movement along the cantilever.

Printer pen carriage support

A memory architecture for supporting mixed-mode memory accesses. A common row address is provided. A first column address for accessing a first column and a second column address for accessing a second column are provided. A first write control signal for specifying one of a write access and a read access for the first column, and a second write control signal for specifying one of a write access and a read access for the second column are also provided. The memory architecture, responsive to these input signals, supports concurrent mixed-mode memory accesses to the first column and a write access to the second column.

Memory architecture for supporting concurrent access of different types

A thermal inkjet printer with firing nozzles perpendicular to the carriage motion has two motors: paper and carriage. These motors, alone or in concert, provide the power to the service station. The service station has separate wiping and pen cleaning functions. The wipers need to move across the pens in a direction that is perpendicular the carriage direction. Through the use of gears, the wipers can be made to clean the pens at the same time that the paper is being advanced and using the same motor source. For capping, the caps are moved into place as the pens come to rest. The motion of the pens themselves could easily push a lever that pushes the caps into place.

Service station for printers having firing nozzles perpendicular to direction of carriage motion

A roller for contacting print media in an image forming device includes a tubular core formed of a first material and having an inner surface and an outer surface, and a sleeve formed of a second material and surrounding a portion of the tubular core. The sleeve includes an inner portion surrounding a portion of the inner surface of the tubular core and an outer portion surrounding a portion of the outer surface of the tubular core. The outer portion of the sleeve has an outer surface for contacting the print media. As such, contact of the print media with the roller is made by the outer portion of the sleeve when the print media is routed through the image forming device.

Cored roller for image forming device

An inkjet printing system includes a print media transport assembly which routes a print medium through the inkjet printing system, a carriage assembly which holds an inkjet printhead assembly and traverse the print medium, and a single motor operatively coupled to both the print media transport assembly and the carriage assembly. As such, the single motor selectively drives both the print media transport assembly and the carriage assembly.

Inkjet printing system using single motor for print media advance and carriage motion

An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity. Additionally, the power management unit maintains the central processing unit in a power mode greater than the power saving mode when either the bus system activity or the telephony interface activity is greater than the predetermined level of activity. An off-hook signal is directly sampled from the modem and provided to activity detection logic within the power management unit. Alternatively, modem interface logic interprets any number of signals provided by the modem to deliver an off-hook signal to the power management unit. Alternatively, telephone interface software includes an off-hook identifier that records the off-hook state of the telephone and an enablement/disablement register in the power management unit is either set or reset. System or user activity is also emulated in order to indicate to the power management unit that activity is occurring within the computer.

Power management system for a computer

A universal asynchronous receiver/transmitter (UART) computer programming interface emulates three-wire interface control. A register select circuit is supplied with address signals from a host CPU and has a plurality of register outputs organized into first and second groups. One of these groups of outputs are those which are required for three-wire operation in communications devices; and these outputs are mapped to the appropriate communications devices or registers. The other group of outputs required for three-wire operation, but with no corresponding function in a communications device, are implemented by means of an UART emulator circuit producing a data output which is coupled to an internal data bus, along with the output of the registers for the communications devices.

Programming interface for a universal asynchronous receiver/transmitter

A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a 'read' of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section. The method of the present invention includes the steps of: a) capturing a status bit in an input flip; b) latching the status bit into an output latch; c) asynchronously enabling the output latch; d) comparing the outputs of the flip-flop and the latch; e) outputting an error signal if the outputs of the flip-flop and the latch are different; and f) outputting the status bit at least if the output of the flip-flop and the latch are the same.

Status register with asynchronous read and reset and method for

An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.

Method and apparatus for reducing power consumption in digital

An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.

Growing community of inventors

Corvallis, OR, United States of America

Laura Elisabeth Simmons