Intrinsity, Inc.

Laura A Potter

Terence M Potter

James S Blomgren

Fritz A Boehm

A static output signal is generated using a static storage element ( ) and transmitted to a NDL gate ( ) over a transmission path ( ) that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to automatically check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tools such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.

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Austin, TX, United States of America

Laura A Potter