Tektronix, Inc.

Laszlo J Dobos

Arthur J Metz

Agoston Agoston

Pavel R Zivny

Donald J Delzer

Maria Agoston

Raymond L Veith

Jan P Peeters Weem

Kenneth J Lester

Klaus M Engenhardt

A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.

Double quadrature with adaptive phase shift for improved phase reference performance

Embodiments of the present invention provide an oscillator having circuitry that measures the power dissipated in a resonator and circuitry that controls the power delivered to the resonator in response to the measured power. In some embodiments, the circuitry that measures the power dissipated in the resonator comprises circuitry that measures the voltage across the resonator, circuitry that measures the current through the resonator, and circuitry that calculates the power dissipated in the resonator based on the measured voltage and current.

Apparatus and method for oscillator resonator power control

Parameters of a spread spectrum clock signal in a communication signal are characterized by acquiring voltage samples of the communication signal at a nominal time location of an edge of the communication signal. The voltage samples are converted to time samples and the difference between the maximum and minimum time values is determined at the nominal time location. A spread spectrum clock magnitude number is generated by dividing the difference between the maximum and minimum time values by the nominal time location of the acquired voltage samples of the spread spectrum clock signal. A spread spectrum modulation profile of a spread spectrum clock signal is estimated by over sampling the time samples using an aliased index value to generate over sampled triangular waveforms representing the spread spectrum clock modulation profile. One of the over sampled triangular waveforms is use to generate the spread spectrum clock modulation profile.

Method of characterizing parameters and removing spectral components of a spread spectrum clock in a communications signal

A method of calibrating a timebase in a digitizing instrument estimates the frequency of the clock signal from the clock generator that clocks a coarse delay counter in a strobe generator. The dynamic range of the interpolator in the strobe generator is defined in digital-to-analog converter code values as a function of the clock signal period. A linear horizontal look-up table of equally spaced digital-to-analog converter code values is generated over the defined dynamic range of the interpolator. Residual nonlinearities of the interpolator over the defined dynamic range of the interpolator are characterized and scaled to digital-to-analog converter code values. The digital-to-analog converter code values of the characterized residual anomalies are combined with the digital-to-analog converter code values of the linear horizontal look-up table to generate a horizontal look-up table having DAC code value compensating for the nonlinearities of the interpolator.

Timebase calibration method for an equivalent time sampling digitizing instrument

A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples. An optional infinite track-and-hold circuit may be used to generate corrected replica phase values that replace the corrected phase values for longer sample delay periods.

Phase startable clock device for a digitizing instrument having deterministic phase error correction

A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to hold, at a selected time during the signal epoch of the respective sinusoidal signals, phase values of the sinusoidal signals. The respective phase values are coupled to an infinite track-and-hold circuit to generate replicas of the phase values. The phase values and the replica phase values are coupled to respective multiplexers that selectively couple the phase values to multipliers during a first time period and replica phase values during a second time period. The output of each multiplexer is coupled to a multiplier that receives one of the phase shifted continuous sinusoidal signals. The output of the multipliers are summed in a summing circuit to generate an output signal with a predetermined stable startup phase relative to the transition. The use of the infinite track-and-hold improves the long-term stability of the output signal from the summing circuit.

Phase startable clock device having improved stability

A signal acquisition and sampling system mounted in an oscilloscope probe includes an input buffer amplifier (30) featuring shunt feedback, offset capability, input bias current compensation, and very low input capacitance. Signal sampling is accomplished by a cascaded pair of differential sampling bridges including a fast track-and-hold stage (40) followed by a slow track-and-hold stage (50). The differential configuration of the bridges features common mode rejection of strobe signal coupling into the signal path and reduces aberrations and voltage droop. The fast track-and-hold stage features Schottky diode switching bridges (42A) and (42B), low value storage capacitors (44A) and (44B), thereby resulting in a fast tracking time. The slow track-and-hold stage features low-leakage diode-connected transistor switching bridges (52A) and (52B) and a FET buffer stage, thereby resulting in fast acquisition of the fast stage output and long hold time for quantization of the sample. A strobe signal is coupled through a cable (72) to a timing generator (80) on integrated circuit (20). The strobe signal causes the fast track-and-hold stage to briefly hold samples of the input signal while simultaneously causing the timing generator to drive the slow track-and-hold stage to quickly acquire the output of the fast stage and hold the acquired value for extended time intervals. The bandwidth of the fast stage is thereby combined with the stability of the slow stage.

Method and apparatus for probing and sampling an electrical signal

A voltage controlled oscillator with temperature compensation and reduced trigger jitter. The temperature compensation is improved by applying an on-chip generated temperature-dependent control voltage to first and second parallel oscillator stages through which the oscillation signal passes. The second stage has a greater signal propagation delay than the first stage. The control voltage determines the signal delay contributed by each stage to the oscillating signal, decreasing the delay in response to a temperature-induced decrease in oscillator frequency and increasing the delay in response to a temperature-induced increase in frequency. The oscillator also includes means for generating oscillations from a predetermined signal phase that is independent of the oscillator phase before triggering.

Phase triggerable oscillator with temperature compensation

A delay element for producing an output signal in response to a change in state of an input signal includes variable gain first and second amplifiers and a delay buffer having a fixed delay. The input signal is applied as input to the first amplifier and the delay buffer while the output of the delay buffer is applied as input to the second amplifier. The outputs of the first and second amplifiers are summed to provide the output signal. When the gain of the first amplifier is high and the gain of the second amplifier is low, the output signal will respond to the change in state of the input signal with minimum delay. When the gain of the first amplifier is low and the gain of the second amplifier is high, the output signal will respond to the change in state of the input signal with maximum delay. The delay in change of state of the output signal in response to a change of state in the input signal may be adjusted with high resolution to a time intermediate between the minimum and maximum delays by adjusting the gains of the first and second amplifiers.

Adjustable delay circuit

A control circuit produces a control voltage for a tunable delay line in response to the magnitude of digital input data. The magnitude of the control voltage output corresponding to any digital input magnitude is independently adjustable to compensate for any nonlinear response of the delay to control voltage input such that the time delay produced by the delay line is substantially a linear function of the digital input to the control voltage source.

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Beaverton, OR, United States of America

Laszlo J Dobos