Fairchild Semiconductor Corporation

Texas Instruments Corporation

Maxim Integrated Products, Inc.

Unitrode Corporation

L&l Engineering, LLC

Laszlo Balogh

Christopher David Bridge

Paul W Latham, Ii

Stewart Gall Kenly

Sombuddha Chakraborty

Michael Lueders

Stefan Herzer

SangCheol Moon

Tuli Luthuli Dake

Philomena Cleopha Brady

Satish Kumar Vemuri

Chenghao Jin

Bonggeun Chung

Maik Peter Kaufmann

GwanBon Koo

William M Andreycak

Jason Guo

Saad Pervaiz

Ritesh Jitendra Oza

A self-biasing circuit for power converters is disclosed. In an example, an apparatus includes a first transistor coupled between an inductor terminal and a ground terminal, and a second transistor coupled between the inductor terminal and a bias terminal. The first transistor has a first control terminal, and the second transistor has a second control terminal. In an example, the first and second transistors are configured to split a current at the inductor terminal. The apparatus further includes a controller having first and second control outputs, where the first control output is coupled to the first control terminal, the second control output is coupled to the second control terminal.

Bias generation for power converter

A controller for a boost power factor correction (PFC) converter. The controller is configured to operate the boost PFC converter in multiple operating modes, including a continuous conduction mode (CCM), a transition mode (TM), and a hybrid mode in which the controller operates the converter in both CCM and TM within a same line cycle. An example controller includes a current control loop and a mode transition circuit. The current control loop is configured to compute an inductor current for each of first and second operation modes, based on a current sample taken, for example, during a boost synchronous rectifier conduction period of the converter. The mode transition circuit includes digital logic circuitry and is configured to generate a pulse indicating that one, two or all three of: zero-voltage switching (ZVS) has been achieved; the synchronous rectifier conduction period is active; and/or one of TM or hybrid mode is active.

Autonomous mode transition for multimode operation in boost PFC converters

An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Wide high voltage swing input comparator stage with matching overdrive

An AC-DC converter includes a main switch that is controlled according to an input AC line voltage. The main switch is allowed to be switched when a level of the input AC line voltage is within a regulation band, and is prevented from being switched when the level of the input AC line voltage is not within the regulation band. The regulation band can be dynamically adjusted based on load condition. The AC-DC converter can be a buck, boost, or buck-boost converter.

Input AC line control for AC-DC converters

In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other. Each synchronization circuit is operable to: receive a first input signal indicative of the beginning of a switching period for the associated variable frequency power converter; receive a second input signal indicative of the end of the switching period for the associated variable frequency power converter; generate a first output signal for directing a pulse width modulation of the associated variable frequency power converter; and generate a second output signal for coordinating a phase relationship with another variable frequency power converter in the system.

Synchronizing frequency and phase of multiple variable frequency power converters

A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching node voltage to a second voltage reference. The second voltage reference is less than the reference potential. The controller calculates delay times based on the first rising edges, the first falling edges, the second rising edges and the second falling edges. The controller generates drive signals for the first switch and the second switch based on a duty cycle and the delay times.

Methods and systems for control of switches in power regulators/power amplifiers

In one embodiment, circuitry is provided for startup of a power converter. The circuitry includes a bias capacitor operable to be charged for providing energy to a controller of the power converter. A divider circuit is coupled to a voltage source. Current flows through the divider circuit. A switch, coupled to the divider circuit, is operable to be turned on and off to divert current flow in the divider circuit for charging the bias capacitor. This provides energy to the controller of the power converter at startup without employing an external bias source or high value bleeder resistor.

Start-up circuitry and method for power converter

Systems and methods control timing of switches in power regulators and power amplifiers. The systems and methods monitor a switch node voltage and obtain rising and falling edges of signals obtained from the monitoring. The systems and methods utilize the rising and falling edges of switch drive signals and predetermined data to obtain delay times for subsequent drive signals.

In one embodiment, a method is provided for reducing soft-start delay and ensuring soft recovery from a short circuit or brown out condition in a power converter. The method includes: providing a feedback signal indicative of the output voltage of the power system at a first input terminal of an error amplifier; providing a soft-start reference voltage at a second input terminal of the error amplifier; comparing the feedback signal against the soft-start reference voltage to generate a control signal for regulating an output voltage of the power converter; sourcing current for pre-charging a soft-start capacitor associated with the soft-start reference voltage, thereby reducing soft-start delay; and sinking current for discharging the soft-start capacitor in the event of a short circuit or brown out condition, thereby providing soft recovery after short circuit or brown out events.

Reducing soft start delay and providing soft recovery in power system controllers

In one embodiment, a method for soft-start in a power converter includes the following: providing a feedback signal indicative of the output voltage of the power system at a first input terminal of an error amplifier in a negative feedback loop of the power converter; providing a reference voltage at a second input terminal of the error amplifier; comparing the feedback signal against the reference voltage to generate a control signal for regulating an output voltage of the power converter; charging a soft-start capacitor coupled to the second input terminal of the error amplifier with a current for establishing the reference voltage; and adjusting the current in response to the control signal so that the error amplifier is prevented from saturation.

Soft-start system and method for power converter

A power supply having a transformer-coupled power converter cascaded with a buck power converter. The transformer-coupled power converter operates in a free-running mode at a nearly 100% maximum duty cycle to convert an input voltage to an intermediate voltage. The buck power converter produces a regulated output voltage from the intermediate voltage. The power supply further includes a pulse width modulation (PWM) controller employing leading-edge modulation of complementary control signals used to control buck switches in the buck converter. The PWM controller is synchronized to primary-side free-running switches of the transformer-coupled power converter by a synchronization signal that is fed-forward across an isolation boundary via a signal transformer. The power supply also may also employ a soft-switching technique to reduce switching losses.

Unique power supply architecture with cascaded converters for large input-to-output step-down ratio

Leading-edge blanking circuits blank the leading edge of a current sense signal generated by sensing circuitry sensing the current through a switching field-effect transistor. A current sensor is employed to sense the magnitude of gate current being provided to the gate of the switching transistor by a driver circuit. A comparator indicates whether the sensed magnitude of the gate current exceeds a predetermined threshold current. A blanking circuit component, such as a transistor connected to ground, is also used. In one blanking circuit, the blanking component forces the current sense signal to zero when the comparator indicates that the gate current of the switching transistor exceeds the threshold current, and otherwise allows the value of the current sense signal to be determined by the current-sensing circuitry. In another blanking circuit, a latch is interposed between the comparator and the blanking component. The latch generates a blanking control signal to control the blanking component. The blanking control signal becomes asserted upon the assertion of a switching-control signal that controls the driver circuit, and becomes deasserted when the comparator indicates that the gate current of the switching transistor has diminished to below the threshold current. In both circuits the blanking interval ends when the gate current has sufficiently diminished, indicating that the initial spike in the switching transistor current has subsided.

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Merrimack, NH, United States of America

Laszlo Balogh