International Business Machines Corporation

Globalfoundries Inc.

Tokyo Electron Limited

Globalfoundries U.S. Inc.

Stmicroelectronics Gmbh

Other

Siemens Aktiengesellschaft

Lockheed Martin Corporation

Infineon Technologies North America Corp.

Globalfoundaries Inc.

Lars W Liebmann

Daniel Chanemougame

Ruilong Xie

Jeffrey Smith

Anton J deVillers

Andre P Labonte

Ioana C Graur

Mark Alan Lavin

Chanro Park

Su Chen Fan

Kandabara N Tapily

Scott Marshall Mansfield

James A Culp

Hui Zang

Sanjay C Mehta

Guillaume Bouche

Bipul C Paul

Geng Han

Mark I Gardner

H Jim Fulford

Min Gyu Sung

Lei Sun

Mark V Raymond

Kanak Behari Agarwal

Steven J Bentley

Fook-Luen Heng

Nicholas V Licausi

Youngtag Woo

Maharaj Mukherjee

Julien Frougier

Cheng Chi

Andreas Knorr

Shayak Banerjee

Subhadeep Kal

Hao Tang

Edward J Nowak

Balasubramanian Pranatharthiharan

Terence B Hook

Yann Mignot

Terry Allen Spooner

John Maxwell Cohn

Sani Richard Nassif

Ulrich Alfons Finkler

Joe Lee

Rama Nand Singh

Allen H Gabor

Steven R Soss

Puneet Harischandra Suvarna

Brent A Anderson

Veeraraghavan S Basker

Hoon Sik Kim

Shreesh Narasimha

Murat Kerem Akarvardar

Gustavo Enrique Tellez

Jason Eugene Stephens

Xu Ouyang

Balasubramanian S Pranatharthi Haran

Lawrence Alfred Clevenger

John H Zhang

Michael Rizzolo

Soon-Cheon Seo

Fee Li Lie

Injo Ok

Hiroaki Niimi

Haiting Wang

Andrew Herbert Simon

Ravikumar Ramachandran

Laertis Economikos

John Edward Barth, Jr

Robert Daniel Clark

John Kenneth DeBrosse

Rasit Onur Topaloglu

Albert Manhee Chu

Emre Alptekin

Shesh Mani Pandey

Cornelius Brown Peethala

Jochen C Beintner

Jason D Hibbeler

Stuart A Sieg

Shuo Zhang

Dongbing Shao

Roger Allan Quon

K Paul Muller

Vimal Kumar Kamineni

Timothy A Brunner

Bartlomiej Jan Pawlak

Michael Straight Hibbs

Henning Haffner

Charan V V S Surisetty

Michael S Gray

Hsien-Ching Lo

Rajeev Malik

Shahid Ahmad Butt

David E Brown

Mahender Kumar

Kevin W McCullen

Burn J Lin

Xintuo Dai

Catherine B Labelle

Jia Zeng

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.

Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)

Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

Tapered device for lateral gate all around devices

Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.

Replacement buried power rail in backside power delivery

Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

Self-aligned method for vertical recess for 3D device integration

A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.

Power wall integration for multiple stacked devices

A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

Interdigitated device stack

An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.

Monolithic formation of a set of interconnects below active devices

A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

Wiring in diffusion breaks in an integrated circuit

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Self aligned buried power rail

An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

Metallization lines on integrated circuit products

A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

High density logic formation using multi-dimensional laser annealing

A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

Integrated high efficiency transistor cooling

Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.

Power delivery network for CFET with buried power rails

A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks

Growing community of inventors

Poughquag, NY, United States of America

Lars W Liebmann