Xilinx, Inc.

Memobit Technologies Ab

Marvell International Limited

Xelerated Ab

Lars-Olof B Svensson

Pär S Westlund

Gunnar Nordmark

Kurt Thomas Boden

Par Westlund

Noel J Brady

Thomas Stromqvist

A cache system includes a computational cache and a computational cache miss-handler. The computational cache is configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands. The computational cache miss-handler is configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache. The memory is external to the cache system.

Cached system for managing state vectors

A hash content addressable memory system includes a hash content addressable memory block (HCB) that is a physical subsystem of the hash content addressable memory system. The first HCB include first bus select logic. The first bus select logic is connected to a plurality of key buses and to a plurality of operation buses. Each key bus from the plurality of key buses and each operation bus from the plurality of operation buses is connected to one and only one client in a plurality of clients. Every client in the plurality of clients is connected to only one key bus from the plurality of key buses and is connected to only one operation bus from the plurality of operation buses.

Content addressable memory system

To produce output from a memory block, a first index is used to access a pointer, a mode select and a function select from a first memory. The pointer, the mode select and the function select are used to produce a second index. The pointer is used to produce the second index when the mode select is a first value. A function is used to produce the second index when the mode select is a second value. The function select identifies a function to be used to produce the second index. The second index is used to access output from a second memory.

Searching memory for a search key

Output is produced from a memory block. A key memory is accessed to produce memory output based on a value of a first index. The memory output includes a stored compressed key and a stored index. A compressed key is produced based on the uncompressed key. The produced compressed key is compared with the stored compressed key. The stored index is output when the stored compressed key matches the produced compressed key.

Memory with compressed key

A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.

System and method for modifying, in a processing pipeline, a length of a data packet in a data block without modifying a length of the data block

The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronization mechanism adapted to synchronize the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronization mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.

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Stockholm, Sweden

Lars-Olof B Svensson