Infineon Technologies Ag

Qimonda Ag

Lars Heineck

Martin Popp

Werner Graf

Stephan Kudelka

Hans-Peter Moll

Jörn Lützen

Peter Baars

Albert Birner

Matthias Goldbach

Mirko Vogt

Henning Haffner

Wolfgang Roesner

Gerhard Enders

Frank Jakubowski

Dirk Manger

Thomas Hecht

Klaus Muemmler

Stefan Jakschik

Till Schlösser

Juergen Holz

Peter Lahnor

Kristin Schupke

Oliver Genz

Bernd Hintze

Arnd Scholz

Momtchil Stavrev

Andreas Orth

Alexander Reb

Stefan Gruss

Johannes Kowalewski

Hans-Georg Fröhlich

Andrei Josiek

Percy Heger

Matthias Handke

Antje Laessig

Johann Steinmetz

Gouri Sankar Kar

Jana Horst

One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Interconnect structure for semiconductor devices

In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

Word line to bit line spacing method and apparatus

In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Method for producing a semiconductor structure

A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Memory cell array and method of forming the same

The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

Method for production of contacts on a wafer

A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate electrode layer, which gate electrodes are arranged in a high packing density in a first section and are assigned to selection transistors of memory cells, and are arranged in a low packing density in a second section and are assigned to transistors of logic circuits. After a processing of the selection transistors, the encapsulated gate electrodes are uncovered in the second section and are subsequently doped in the same way in each case simultaneously with the respectively assigned source/drain regions. Together with a subsequent siliciding of the gate electrodes and of the source/drain regions, the performance of the transistors in the second section is significantly increased with little additional outlay.

Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate

Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Method for fabricating a contact hole plane in a memory module

A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Semiconductor trench structure

A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

Method for fabricating a trench capacitor with an insulation collar

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Dresden, Germany

Lars Heineck