National Semiconductor Corporation

Silicon Wave, Inc.

Lars G Jansson

Lars Henrik Mucke

Christopher Dennis Hull

Roy L Yarbrough

Michael G Ward

Ernest D Haacke

A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or &ldquo;binary&rdquo; varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C,; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C,. The capacitance of the binary capacitor can be changed from C,to C,simply by changing the polarity of the applied D.C. voltage from a positive to a negative value. A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally controlled capacitor. The digitally controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented.

Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device

A crystal oscillator apparatus is described that has a wide dynamic frequency range and that is capable of supporting a broad range of crystal types. The present invention reduces the unwanted side effects that are associated with the prior art crystal oscillator designs, such as the clipping of signals, the introduction of signal distortion and unwanted signal harmonics. The present invention reduces the total wasted loop gain of the oscillator while also reducing the amount of integrated circuit real estate required to implement the crystal oscillator. The crystal oscillator apparatus of the present invention preferably comprises a crystal resonator circuit, an inverting amplifier, a bias circuit, a reference circuit, and a peak detector circuit. The present invention takes advantage of Automatic Gain Control (AGC) design techniques. The gain of the present crystal oscillator is automatically regulated using a closed loop circuit design. The present invention advantageously utilizes a peak detector circuit in combination with a reference circuit. The peak detector compares a reference signal with an amplified and inverted oscillation signal produced by a crystal resonator, and generates a feedback signal as a result of the comparison. The feedback signal controls a bias circuit that, in turn, controls the amplified inverted oscillation signal. The preferred embodiment of the present invention preferably comprises MOSFETs, resistors and capacitors implemented on a single integrated circuit device. By implementing the present inventive crystal oscillator on a single integrated circuit device, the deleterious effects introduced by temperature variations are advantageously reduced or nullified.

Crystal oscillator with peak detector amplitude control

A method and apparatus for fully integrating a Voltage Controlled Oscillator (VCO) on an integrated circuit. The VCO is implemented using a differential-mode circuit design. The differential-mode implementation of the VCO preferably comprises a differential mode LC-resonator circuit, a digital capacitor, a differential pair amplifier, and a current source. The LC-resonator circuit includes at least one tuning varactor and two high Q inductors. The tuning varactor preferably has a wide tuning capacitance range. The tuning varactor is only used to &ldquo;fine-tune&rdquo; the center output frequency f,of the VCO. The center output frequency f,is coarsely tuned by the digital capacitor. The VCO high Q inductors comprise high gain, high self-resonance, and low loss IC inductors. The IC VCO is fabricated on a high resistivity substrate material using a trench isolated guard ring. The guard ring isolates the fully integrated VCO, and each of its component parts, from RF signals that may be introduced into the IC substrate by other devices. By virtue of the improved performance characteristics provided by the digital capacitor, the analog tuning varactor, the high Q inductor, and the trench isolated guard ring techniques, the inventive VCO is fully integrated despite process variations in IC fabrication.

Method and apparatus for fully integrating a voltage controlled oscillator on an integrated circuit

Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors

A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node of an emitter follower transistor element is coupled to a collector node of the input transistor circuit in an inverting coupling. The emitter node is coupled to a base node of the phase splitter transistor element for sourcing base driven current to the phase splitter transistor element in response to data signals at the input. The emitter follower provides transient 'overdrive' for fast turn on of the phase splitter. A first clamp circuit between the base node of the emitter follower transistor element and the low potential power rail clamps the base node at a low potential level when the emitter follower transistor element is relatively non-conducting and establishes the input threshold voltage level. A second clamp circuit coupled to the base node of the emitter follower transistor element clamps the base node at a high potential level for limiting base drive current to the phase splitter transistor element from the emitter follower transistor element. The second clamp circuit limits saturation of the phase splitter transistor element and improves switching speed. The second clamp circuit is preferably coupled between the base node of the emitter follower transistor element and a collector node of the phase splitter transistor element and includes a 'programmable' resistor voltage drop component for limiting operation of the phase splitter transistor element to the desired operating region.

High speed TTL buffer circuit and line driver

A TTL inverter buffer circuit is provided with a switched current that produces hysteresis in the threshold values. The current is switched on by a control circuit when the input logic is low and off when the logic is high. The control circuit receives its sense from the logic state so that when the input logic is low a high threshold is created and when the input logic is high a low threshold is created. The difference is the circuit hysteresis voltage which is dependent upon the switched current and a resistor.

High speed inverting hysteresis TTL buffer circuit

A translator-translator logic (TTL) to emitter coupled logic or current mode logic (ECL/CML) input buffer and translator circuit provides temperature compensated input and threshold signal voltage levels to a translator circuit ECL gate for improved operation of the translator circuit. A threshold clamp circuit is coupled between an on-chip band-gap bias generator and the base node of the reference transistor element of the translator circuit ECL gate. The threshold clamp circuit maintains a substantially fixed temperature compensated reference voltage or threshold voltage level at the base node of the reference transistor element, referenced to the temperature compensated current source voltage level V.sub.cs from the bias generator. An input clamp circuit also references the logic high signal voltage level V.sub.TH at the base node of the ECL gate input transistor element to V.sub.CS.

TTL to ECL/CML translator circuit

An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region. The circuit functions of reference voltage level shifting and of operating region translating are thereby separately performed by separate components. The TTL gate input is a phase splitter transistor element. A resistor pulldown discharges the phase splitter transistor element. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp. More generally, an overdrive and anti-saturation clamp circuit provides high speed switching of the phase splitter or other TTL switching transistor element.

High speed ECL/CML to TTL translator circuit

An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation threshold operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate for shifting the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate. The circuit functions of reference voltage level shifting and of operating region translating are thereby separated. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp circuit. More generally, an overdrive and anti-saturation clamp control circuit provides high speed switching of a phase splitter transistor element, pulldown transistor element, or other TTL switching transistor element for generalized application in TTL internal and output gates and buffers. The overdrive and clamp control circuit provides a 'programmable' base-collector clamp voltage for operation of TTL switching transistor elements in 'soft' saturation, in threshold saturation, or entirely out of saturation for operation of linear TTL circuits.

TTL gate current source controlled overdrive and clamp circuit

Dual phase splitter transistor elements, an output phase splitter transistor element and a secondary phase splitter transistor element, are coupled in current mirror configuration in a TTL output buffer circuit. The output phase splitter transistor element is coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements. The collector of the secondary phase splitter transistor element is coupled in a supplemental circuit which can have a variable load without direct connection to the pullup transistor element and output. A low impedance current sourcing active transistor element is coupled in emitter follower configuration at the collector node of the secondary phase splitter transistor element for supplying mirroring current through the emitter of the secondary phase splitter transistor element to reduce current hogging at the dual phase splitter transistor elements. The current sourcing transistor element is coupled in parallel with the supplemental circuit thereby providing a variable current which varies inversely with the collector current supplied by the supplemental circuit. The invention is applied in a JK flip flop circuit as the output buffer circuits with the collector of the secondary phase splitter transistor element coupled to the cross feedback circuit. The cross feedback transistor element in the cross feedback circuit is therefore isolated from the pullup transistor element and output avoiding feedback transistor breakdown when the output is at high potential. The current sourcing transistor element prevents current hogging between the dual phase splitter transistor elements.

Growing community of inventors

Long Island, ME, United States of America

Lars G Jansson