Infineon Technologies Ag

Qimonda Ag

Lars Dreeskornfeld

Franz Hofmann

Michael Specht

Tobias Mono

Arnd Scholz

Matthias Goldbach

Stefan Slesazeck

Johannes Kretz

Johannes Luyken

Ulrich Dorda

A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Method of manufacturing integrated circuits including a FET with a gate spacer and a fin

The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (); forming an active region () on the substrate a fin-like channel region (&#x2033;). Formation of the fin-like channel region (&#x2033;) has the following steps: forming a hard mask (S-S) on the active region (); anisotropic etching of the active region () using the hard mask (S-S) forming STI trenches (G-G) having an STI oxide filling (); polishing-back of the STI oxide filling (); etching-back of the polished-back STI oxide filling (); selective removal of components of the hard mask forming a modified hard mask (S-S); anisotropic etching of the active region () using the modified hard mask (S-S) forming widened STI trenches (G-G'), the fin-like channel regions (&#x2033;) of the active region () remaining for each individual FinFET transistor.

Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement

An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Integrated circuit and method of manufacturing an integrated circuit

Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.

Nonvolatile memory cell arrangement

Growing community of inventors

Dresden, Germany

Lars Dreeskornfeld