Qimonda Ag

Infineon Technologies Ag

Nanoplus Nanosystems and Technologies Gmbh

Lars Bach

Wolfgang Kaiser

Franz Hofmann

Josef Willer

Nicolas Nagel

Michael Specht

Thomas Mikolajick

Dominik Olligs

Doris Keitel-Schulz

Veronika Polei

Thomas Melde

Christoph Friederich

Johann Peter Reithmaier

Torsten Mueller

An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method

In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore, the contact structure may be arranged such that the length direction of the contact structure forms a non-zero angle with the first direction of the active area.

Integrated circuits having a contact structure having an elongate structure and methods for manufacturing the same

The present invention provides a manufacturing method for an integrated circuit and a corresponding integrated circuit. The integrated circuit comprises a plurality of first devices, each first device including a charge storage layer and a control electrode comprising a plurality of layers; and a plurality of second devices coupled to at least one of the plurality of first devices, each second device including a control electrode comprising at least one layer different from said plurality of layers.

Integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit

Disclosed is a semiconductor laser in which the substrate comprises at least three independent functional sections in the direction of light wave propagation, said functional sections serving different functions and being individually triggered by means of electrodes via electrode leads. An intensification zone, a grid zone, and a phase adjustment zone are provided as functional sections. The light wave is optically intensified in the intensification zone while the phase of the advancing and returning wave is adjusted in the phase adjustment zone. The grid zone is used for selecting the wavelength and adjusting the intensity of coupling between the intensification zone and the phase adjustment zone.

Multisectional laser

An interlayer is disposed on a pattern surface of a substrate. A buried hard mask may be provided on the interlayer. The buried hard mask includes a template opening having a template length along a line axis and a template width perpendicular thereto. The buried hard mask is filled with a fill material. A top mask is provided above the filled buried hard mask. The top mask includes a trim opening crossing the template opening and having a trim width along the line axis that is smaller than the template length. By etching the fill material and the interlayer using the top and buried hard mask a process section of the pattern surface may be exposed such that a target length and width of the process section result from the template and the trim widths. The planar dimensions of the process section may be decoupled from each other.

Hard mask arrangement, contact arrangement and methods of patterning a substrate and manufacturing a contact arrangement

A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided.

Integrated circuit and methods of manufacturing a contact arrangement and an interconnection arrangement

Disclosed is a semiconductor laser () in which the substrate () comprises at least three independent functional sections () in the direction of light wave propagation (A), said functional sections () serving different functions and being individually triggered by means of electrodes () via electrode leads (). An intensification zone (), a grid zone (), and a phase adjustment zone () are provided as functional sections. The light wave is optically intensified in the intensification zone () while the phase of the advancing and returning wave is adjusted in the phase adjustment zone (). The grid zone () is used for selecting the wavelength and adjusting the intensity of coupling between the intensification zone () and the phase adjustment zone ().

A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional 'contact to interconnect' structures.

Method for forming a semiconductor product and semiconductor product

A semiconductor memory () having a plurality of memory cells (), the semiconductor memory () having a substrate (), at least one wordline () and first () and second lines (). Each memory cell () of the plurality of memory cells () includes a fin () of semiconductor material, the fin () having a top surface (), first () and second () opposing sidewalls and first () and second () opposing ends. The fin () extends along a first direction (X). Each memory cell () also includes a charge-trapping layer () disposed on the first () and second () sidewalls of said fin (), a patterned first insulating layer () disposed on the top surface () of the fin (), wherein the first insulating layer () abuts the top surface () of the fin () and the charge-trapping layer (). Each memory cell () also includes a first doping region () coupled to the first end () of said fin () and a second doping region () coupled to the second end () of the fin ().

Growing community of inventors

Ullersdorf, Germany

Lars Bach