Advanced Micro Devices Corporation

Maxim Integrated Products, Inc.

Larry Yu Wang

Steven C Avanzino

Jeffrey Allan Shields

Arkadii V Samoilov

Stephen Keetai Park

Tyler Parent

Paul Raymond Besser

Bharath Rangarajan

Albert M Bergemont

Karsten Wieczorek

Yi He

Wei Zhao

Guarionex Morales

Craig S Sander

Nicholas John Kepler

Anna Maria Minvielle

Steven K Park

Che-Ping Chen

Sean Lynch

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Semiconductor device having a through-substrate via

A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.

Dynamic trim method for non volatile memory products

A method and article of manufacture of a semiconductor device having a cleaned source/drain surface and substantially uniform cobalt silicide deposited thereon. The method of the invention includes a precursor conventional step of an argon ion pre-sputter step which generally cleans the semiconductor device surfaces but ensures a resputtering of SiO to form SiO species deposits on the source/drain surface of the device. An in situ treatment using silicon hydride species causes reduction of the SiO species leaving a cleaned residual silicon which can accept a cobalt deposition to form a desired cobalt silicide layer on the source/drain surface.

Use of gaseous silicon hydrides as a reducing agent to remove re-sputtered silicon oxide

A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of a semiconductor device. Silicon nitride disposable spacers are formed over the metal layer in the region of the sidewall spacers previously formed on the sidewalls of the gate. A silicon cap layer is deposited over the metal layer and the disposable spacers. Rapid thermal annealing is performed to form the high-ohmic phase of the salicide, with the disposable spacers preventing interaction and between the cobalt and the silicon in the area between the gate and the source/drain junctions along the sidewall spacers. The silicon cap layer provides a source of silicon for consumption during the first phase of salicide formation, reducing the amount of silicon of the source/drain junctions that is consumed.

Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption

Embodiments of the invention comprise a new device and technique to realize an improved coupling ratio integrated circuit device. This improvement is achieved by increasing an overlap portion between the first and second polysilicon layers, so as to increase the effective coupling ratio between the layers. In the embodiments of the present invention, a relatively tall or large portion of oxide is formed over at least a portion of each of a plurality of shallow trench isolation regions. This oxide is then utilized to provide a larger first polysilicon layer surface area, but without substantially increasing the tunnel oxide layer surface area. Then, a dielectric interlayer is formed upon the surface of the first polysilicon layer, and next, a second polysilicon layer is formed upon the dielectric interlayer. This increased overlap portion thus allows for an increased coupling ratio. Further, the coupling ratio may be tailored by adjusting either or both of the first and second polysilicon layer surface areas without requiring a substantial change in the tunnel oxide layer surface area.

Flash memory device and fabrication method having a high coupling ratio

A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

Method of forming rectangular shaped spacers

An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

Method to fabricate a high coupling flash cell with less silicide seam problem

The quality of an ultra thin gate oxide film, particularly at the edges of a shallow trench isolation structure, is improved employing a double sacrificial oxide technique. After trench filling and planarization, the pad oxide layer thickness is increased during trench fill densification in an oxidizing atmosphere. The pad oxide is then removed exposing the substrate surface and trench edges. A second sacrificial oxide is formed consuming part of the substrate surface. The second sacrificial oxide is then removed along with defects in the substrate surface prior to gate oxide and gate electrode formation.

Method of forming trench isolation with high integrity, ultra thin gate

The separate formation of alignment marks and manufacturing a semiconductor device comprising photolithographically printing circuit patterns is avoided by utilizing trenches formed when etching to form shallow isolation trenches, thereby increasing manufacturing throughput and reducing costs. Embodiments include utilizing alignment trenches having a depth of about 2,400.ANG. to less than about 4,000.ANG., e.g., 3,000.ANG., formed substantially simultaneously with forming isolation trenches having substantially the same depth as the alignment trenches.

Method for making shallow trench marks

A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by using actual mask data as a reference. The invention discloses an algorithm which measures the geometric and relative separation distances of the active areas and performs the necessary merging, deletion and differential biasing to produce the planarization mask which has relaxed geometric boundaries, thereby allowing low cost and simplified manufacturing.

Generation of a loose planarization mask having relaxed boundary

A method of rounding corners of isolating trenches formed in a substrate with a planar surface includes a first step of forming a masking material on the planar surface. Edges of the masking material are offset from the corners of the isolating trenches. The second method step includes growing an oxide on an exposed portion of the substrate under high temperature. The oxidation under high temperature causes the corners of the isolating trenches to become rounded.

Method for formation of offset trench isolation by the use of disposable

A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.

Method of forming a zero layer mark for alignment in integrated circuit

A method of electrically measuring thin oxide thickness by tunnel voltage in a device under test includes the steps of applying a predetermined value of current density through the device under test, measuring voltage developed across the device under test, and calculating the oxide electrical thickness through a predetermined calibration curve. This method is suitable for incorporation into an automatic tester for fast and high volume data collection. This technique also has higher resolution and accuracy than measurements obtained optically.

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San Jose, CA, United States of America

Larry Yu Wang