Montage Technology Group Limited

Montage Technology (shanghai) Co., Ltd.

Montage Technology Inc.

Larry Wu

Gang Shan

Howard Chonghe Yang

Xiaomin Si

Yibo Jiang

Stephen Tai

Zhen-Dong Guo

Jie Zhang

Swee Ann Teo

Gang Yan

Zhendong Guo

Xiaorong Ye

A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.

Registered DIMM memory system

A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.

Method for generating read enable signal and memory system using the method

Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Calibration of read/write memory access via advanced memory buffer

Integrated circuits have expanded a set of custom registers and a read mechanism for control registers. One embodiment includes a circuit having a first set of registers; a second set of registers to be written via one or more write operations addressed to one or more registers of the first set; and a read controller coupled with the first and second sets of registers, the read controller to selectively output a portion of data stored in the first and second sets of registers based on data stored in one or more registers of the second set. In one embodiment, the circuit further includes a logic block; and a multiplexer to select from an output of the logic block and an output of the read controller as an output of the circuit based on the data stored in the one or more registers of the second set.

Register read mechanism

Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

On-die termination circuit

A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

Clock and data recovery

A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Memory interface to bridge memory buses

A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers

High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

Growing community of inventors

Shanghai, China

Larry Wu