International Business Machines Corporation

Globalfoundries Inc.

Larry Wissel

Terence B Hook

Michael Richard Ouellette

Tak H Ning

Mark Charles Hakey

John Atkinson Fifield

Kenneth Parker Rodbell

David James Hathaway

Albert Manhee Chu

Peter Anton Habitz

John Maxwell Cohn

Jason D Hibbeler

James Spiros Nakos

William Eric Hall

Darren Lane Anand

Scott Whitney Gould

Paul Steven Zuchowski

David E Lackey

Michael Sperling

Alvar Antonio Dean

Donald Lawrence Wheater

Ronald Dennis Rose

Susan K Lichtensteiger

Terrance John Zittritsch

Roger Paul Gregor

Jeffery Howard Oppold

Joel T Ficke

Allan Robert Bertolet

William R Griffin

Henry H K Tang

Jose L P Neves

Paul H Bergeron

Keith M Carrig

James J Engel

Harold E Reindel

John G Petrovick, Jr

William F Smith

Steven P Koch

Paul J Sulva

Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified to bring non-compliant periphery chip regions into compliance, in response to the determination that the portion of the first chip layout inside the tile area fails to comply with the one or more design rules. A multi-chip wafer is fabricated that includes the chip layouts.

Checking wafer-level integrated designs for rule compliance

Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified, responsive to the determination that the first chip layout within the tile area fails to comply with the one or more layout design rules, to bring non-compliant periphery chip regions into compliance. It is determined that the portion of the first chip layout within the tile area complies with the one or more design rules after modifying the first chip layout. A multi-chip wafer is fabricated that includes the chip layouts.

Methods and systems for checking a wafer-level design for compliance with a rule include determining whether each chip layout out of multiple chip layouts complies internally with one or more layout design rules. A tile area is determined, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined whether portions of the plurality of chip layouts inside the tile area comply with the one or more layout design rules. The chip layouts are modified, if chip layout area within the tile area fails to comply with the design rule, to bring non-compliant periphery chip regions into compliance.

Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a set of chip layouts. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of properties of the respective interconnected nets. Chip layouts related to virtual ensembles that do not comply with a design rule are modified to bring non-compliant virtual ensembles into compliance.

Checking wafer-level integrated designs for antenna rule compliance

Methods and systems for checking a wafer-level design for compliance with a rule include identifying nets that cross chip boundaries for each of a plurality of chip layouts. Net properties are determined for each of the identified nets. Interconnected identified nets are combined into one or more virtual ensembles having properties defined by a sum of the properties of the respective interconnected nets. Each virtual ensemble is evaluated for compliance with a design rule. The chip layouts related to virtual ensembles that do not comply with the design rule are modified to bring non-compliant virtual ensembles into compliance.

A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

Physically unclonable function implemented through threshold voltage comparison

A design structure for an integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop. The second delayed version of the clock signal drives the third flip-flop to monitor the second flip-flop delay, the possible 'pass set-up' state, and 'pass hold' state outputs are determined for the second flip-flop based on a final test state of the second and third flip-flops.

Structure for integrated circuit for measuring set-up and hold times for a latch element

A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.

Memory column redundancy scheme

A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.

Method and system of modeling leakage

A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.

Design structure for improved memory column redundancy scheme

An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.

Unclocked eFUSE circuit

Circuitry that includes a voltage controller () for providing a variable gate signal () for controlling the gate of a programming transistor () used in conjunction with programming an electrically programmable fuse ('eFuse') () of an integrated circuit (). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner () for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.

Circuitry and method for programming an electrically programmable fuse

An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.

Low voltage programmable eFuse with differential sensing scheme

A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a 'don't care' state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

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Williston, VT, United States of America

Larry Wissel