International Business Machines Corporation

Other

Larry Wayne Loen

Edward John Silha

John Matthew Santosuosso

Michael Joseph Corrigan

Roy L Hoffman

Frank G Soltis

Randy Keith Rolfe

Daniel Frank Moertl

Gary Scott Delp

Bruce Leroy Beukema

Jeffrey Douglas Brown

Michael Raymond Trombley

Andrew Henry Wottreng

Scott Douglas Clark

Kent Harold Haselhorst

Michael Joseph Carnevale

Leon Edward Gregg

Marc Alan Auslander

Martin Edward Hopkins

Glen R Mitchell

Abdo Esmail Abdo

Philip Braun Winterfield

Merle E Houdek

Steven L Jones

Robert W Collins

William T Burke

Theodore J Friedl

David Robert Russell, Jr

An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus. The enhanced mechanism enables a variable amount of parallelism to be implemented and yet provides correct program execution even if less parallelism is available than ideal for a given computer program.

Utilizing a bidding model in a microparallel processor architecture to allocate additional registers and execution units for short to intermediate stretches of code identified as opportunities for microparallelization

In processing a query including a selection criterion on one or more attributes of a relation, a prior statistic generated for a prior different selection criterion on the same one or more attributes of the relation, may be revalidated for use in processing the query, based upon a measure of the entropy of the one or more attributes of the relation. In this way, the re-validation of statistics may be performed more efficiently. Furthermore, attribute groups of a relation for which multi-dimensional indexes are to be formed, are identified by evaluating the correlation of attribute values within tuples of the relation and determining that the correlation of attribute values within tuples of the relation exceeds a threshold.

Estimation and use of access plan statistics

An apparatus and method authenticate computed results in a public distributed computing environment without the need for fully recomputing the results. The work unit is operated on by client code that computes one or more partial results along with the completed result. When the results are returned to the server, the server may decide to have a trusted computer system process the same work unit to compute the partial result according to a defined acceptance policy. In addition, the work unit name, user identity and current date are encrypted using a time-sensitive key. Should the server detect a problem with the results (e.g., decrypted work unit name does not match, recomputed partial result does not match), the results may be rejected according to a defined rejection policy. In this manner, it becomes very difficult to fool a server into thinking a work unit has been processed when it has not.

Authenticating computed results in a public distributed computing environment

The present invention is a method and system of reusing a local memory space in a computer. In accordance with the invention an incoming stream of computer instructions is analyzed by an executable module to determine the presence of a first predetermined operator in the stream of computer instructions. If the first predetermined operator is present, the present invention determines the value of a parameter following the first operator in the stream and the executable module interposes a second operator in place of the first operator and reuses a local memory space to store an instance of the parameter in the memory space in response to the execution of the second operator.

Compilation method and system to reuse memory storage instead of allocating it

The present invention is a computer implemented method and system for minimizing contention for a shared resource between a plurality of processes executing computer instructions that are associated with said shared resource. The method analyzes at least one of said processes of computer instructions and determines whether at least one of said processes modifies said shared resource. If at least one of said processes does not modify said shared resource, the method controls access to said shared resource by at least one said process.

Safe strength reduction for Java synchronized procedures

An apparatus, program product, and method of processing a request to create an immutable object reuse an existing immutable object in appropriate circumstances to represent redundant data without the necessity for creating an additional immutable object. Prior to creating a new object in response to a request to create an immutable object, a determination is made as to whether a matching immutable object already exists that has the same contents as the requested immutable object. If so, creation of a new object is inhibited, and a reference to the matching immutable object is returned in response to the request.

Reuse of immutable objects during object creation

A computer system and method for use with the computer system to dynamically adapt to a data structure layout other than its own. The data may be an incoming data stream from outside or may be stored within its main memory. Between the transmitting and the receiving CPU there must be an understanding of the conceptual level and format of the data which is transferred. A prefix word in which details of the data structure layout is encoded is generated. The prefix word is appended to the data and transmitted to another CPU or used by the same CPU. Upon receipt of the data, the prefix word is read and decoded and the receiving CPU can dynamically adapt to details of the data structure layout in order to use the data which was generated and transmitted in a heretofore unknown data structure layout. The prefix word may be a Unicode reserved character of the form FExxyyFF or FFyyxxFE wherein FExxyyFF represents the same endianness, preferably big endian, and FFyyxxFE represents the other endianness, preferably little endian. Once endianness is resolved, then the position of xxyy is unambiguously known and specific features of the data structure layout, such as integer and pointer sizes, rounding/padding rules, byte alignment, bit alignment, etc. are encoded in an agreed-upon bit sequence. Thus, a method and a computer which can dynamically adapt to an unknown data structure is presented.

Generalizing data streams to overcome differences in word length and byte order

An apparatus, program product, and method perform address translation on a process-local, rather than system-wide, basis in a single-level store virtual memory management system using a plurality of process-local address translation data structures that are individually associated with particular software processes executing on a computer. By performing address translation on a process-by-process basis, many of the security concerns associated with system-wide address translation, e.g., attempting to access a virtual address for memory that has not been allocated for the associated process, are significantly reduced from the standpoint of accessing an address translation data structure, since it can be presumed that all of the information in a process-local address translation data structure was previously authorized for the process when added to the data structure. Relatively simpler and faster security checks can then be performed in association with accessing a process-local address translation data structure to minimize the processing delays associated with such accesses. In addition, with such a configuration, any additional security issues can be handled in additional fault handling processing that is executed less frequently than accesses to address translation data structures, such that such additional security processing has a reduced impact on system performance.

Single-level store computer incorporating process-local address translation data structures

A conventional bi-endian computer system is enhanced to include mixed-endian mechanisms that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian mechanisms automatically format the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian format. The mixed-endian mechanisms also format big and little endian instructions such that they can execute on the same computer system. The mixed-endian mechanisms also include two memory management mechanisms, a single aliased memory management mechanism and a double aliased memory management mechanism. Each memory management mechanism provides cross-endian data sharing.

Mixed-endian computer system that provides cross-endian data sharing

The present invention is a method of allocating memory storage in a memory storage space commonly shared by multiple processors. The method allocates a minimum apparent memory storage space equal to one cache line and in response to storing an object, said object occupying a memory storage space equal to less than one cache line, the method determines the value of a variable. The method then allocates said memory storage space for said object based on the value of said variable and updates said variable.

Multiprocessor scaleable system and method for allocating memory from a heap

A conventional bi-endian computer system is enhanced to include mixed-endian mechanisms that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian mechanisms automatically format the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian format. The mixed-endian mechanisms also format big and little endian instructions such that they can execute on the same computer system.

Mixed-endian computing environment for a conventional bi-endian computer

A conventional bi-endian computer system is enhanced to include mixed-endian mechanisms that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian mechanisms automatically format the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian formate. The mixed-endian mechanisms also format big and little endian instructions such that they can execute on the same computer system.

A mixed-endian computer system enhanced to manage I/O DMA without a software DMA performance penalty. A mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian system, as enhanced, performs one of two well-defined DMA operations based on control bits either in the DMA control register or in a bit vector associated with each page of processor storage. This invention also describes means for treating I/O registers as if they were of the endian of the executing processor, instead of the more typical need to have the register operate in a particular endian.

Independent control of DMA and I/O resources for mixed-endian computing

A synchronous interrupt handler for a processing system executing multiple modes of operation employs a minimum number of lines of interrupt handler code written to execute at the 'zeroth' level, is combined with a virtualized interrupt vector table. An identical zeroeth level handler is inserted at each of the processor's interrupt vector entry pints. These short code sequences are the first to gain control following an interrupt. They are handwritten in the platform's native instruction set to be mode-independent. For example, if the platform's processor does not alter the 'endianness' of the machine state following an interrupt, the 'zeroeth level' code must be written for endian neutrality; likewise, for 32/64-bit mode, etc. For each mode of operation, there is created a Virtualized Vector Table to represent the proper interrupt handlers for each physical interrupt level. Each task data structure, implicitly reflecting its unique mode of operation, contains a pointer to its virtualized vector table. The zeroeth-level handlers then extract the virtualized vector table reference for their own interrupt level and indirectly pass control to the preloaded table value.

Integrating multi-modal synchronous interrupt handlers for computer

A data compression utilization method and apparatus are provided for a computer main store. An amount of unused memory in the computer system main store is dynamically calculated and compared with a plurality of predefined threshold values. One interrupt of a plurality of predefined interrupts is selectively generated responsive to the compared values. Then the usage of the computer system main store is adjusted responsive to the generated interrupt.

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Rochester, MN, United States of America

Larry Wayne Loen