Memc Electronic Materials, Inc.

Corner Star Limited

Larry W Shive

Brian Lawrence Gilmore

Saeed Pirooz

Puneet Gupta

Igor J Malik

Dale A Witte

Gordon P Hampton

James P Davidson

Gary L Anderson

Rituraj Nandan

Andrew P Lunday

Omid Rezvanian

M Rao Yalamanchili

James C Lenk

Edward Calvin

Carissima M Vitus

Kari B Myli

A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.

Systems and methods for manufacturing diamond coated wires

A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Process for annealing semiconductor wafers with flat dopant depth profiles

Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.

Methods for producing smooth wafers

Processes for the purification of silicon carbide structures, including silicon carbide coated silicon carbide structures, are disclosed. The processes described can reduce the amount of iron contamination in a silicon carbide structure by 100 to 1000 times. After purification, the silicon carbide structures are suitable for use in high temperature silicon wafer processing.

High purity silicon carbide structures

Method for purifying silicon carbide coated structures

A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.

Process for metallic contamination reduction in silicon wafers

A wafer boat for use in heat treatment of semiconductor wafers in a vertical furnace comprises support rods extending generally vertically when the wafer boat is placed in the vertical furnace. Fingers are supported by and extend along vertical extent of the support rods. Wafer holder platforms are adapted to be supported by groups of fingers lying in generally different common horizontal planes. The fingers are adapted to underlie the wafer holder platforms and support the platforms at the support locations. The fingers and wafer holder platforms each have a respective first overall maximum thickness. The support location of at least one of the fingers and the wafer holder platforms have a second maximum thickness less than the first overall maximum thickness.

Semiconductor wafer boat for a vertical furnace

A process is disclosed for making a silicon wafer with low and uniform surface stress by growing at least approximately 8 angstroms of silicon oxide thereon to produce a wafer for use as a control wafer in ion implantation. The process involves the steps of (a) subjecting a feed wafer substantially free of oxide or having less than approximately 4 angstroms of silicon oxide thereon to hydrogen termination of the silicon surface; or (b) subjecting such a feed wafer to said hydrogen termination followed by subjecting the resulting wafer to treatment with an oxidant having a standard reduction potential less than approximately 1.77 volts; the wafer resulting from either step (a) or (b) having a TWO reading less than approximately 30 across the entire wafer.

Process for making wafers for ion implantation monitoring

A process for removing a metallic contaminant from a nonpatterned silicon wafer. In the process, the wafer is annealed by immersing it for at least about 0.1 hours in an acidic solution which is heated to a temperature of at least about 125&deg; C. in order to diffuse the metal to the surface of the wafer. As the diffused metal reaches the wafer surface, it is oxidized and complexed by the acidic solution and removed from the wafer surface.

Process for the removal of copper and other metallic impurities from silicon

A process for cleaning a final polished semiconductor wafer in a single operation (i.e., following final polishing, a process or action is directed at the wafer which includes drying the wafer only once, thereby yielding a polished wafer surface substantially free of contaminants). The process comprising contacting the polished wafer with an aqueous solution comprising an oxidizing agent to oxidize organic carbon on the surface of the polished wafer. After oxidizing the organic carbon, immersing the polished wafer in an megasonically agitated alkaline cleaning solution to reduce the surface concentration of contaminant particles exceeding 0.2 &mgr;m in diameter. Withdrawing the polished wafer from the alkaline cleaning solution and rinsing it with deionized water. After rinsing, immersing the polished wafer in an acidic cleaning solution to reduce the surface concentration of contaminant metal atoms. Withdrawing the polished wafer from the acidic cleaning solution and immersing it in an ozonated aqueous bath. Withdrawing the polished wafer from the aqueous bath and drying the wafer. The process is further characterized by the absence of a step in which the surface of the polished wafer is dried between oxidizing organic carbon on the surface and immersing the wafer in the ozonated aqueous bath.

Single-operation method of cleaning semiconductors after final polishing

Processes for cleaning a silicon body and for controllably decreasing the thickness of a silicon dioxide layer overlying a silicon substrate are disclosed. The processes comprise chemically etching a silicon dioxide layer with a dilute etchant in the presence of a megasonic field. The concentration of the etchant is preferably less than its diffusion-rate-limiting threshold concentration at a given temperature. When aqueous alkaline hydroxyl ion etchants are employed, the concentration of etchant is preferably less than about 300 ppm by weight relative to water. The etching is discontinued before the silicon substrate is exposed to the etchant. The etch rate is controlled to within about 2.times.10.sup.-5 .mu.m/min (0.2 .ANG./min) of a target etch rate which ranges from about 3.times.10.sup.-5 .mu.m/min (0.3 .ANG./min) to about 4.times.10.sup.-4 .mu.m/min (4.0 .ANG./min). A simpler, more cost-effective chemical process for robustly cleaning silicon bodies or for producing very thin gate oxides is achieved.

Control of SiO.sub.2 etch rate using dilute chemical etchants in the

A box handling apparatus having particular application in the packaging of semiconductor wafers, includes a box opening assembly which can unlatch a lid from a bottom of the box and separate the lid from the bottom. Arms can grip an article, such as a wafer cassette, in the bottom of the box and lift it out. The cassette can be loaded, or wafers already in the cassette unloaded. The apparatus can replace the loaded cassette in the bottom of the box and latchingly re-engage the lid.

Box handling apparatus and method

A gettering agent for gettering metals from a solution. The gettering agent has a surface layer of SiO.sub.2 which is greater than 15 angstroms in thickness.

Gettering agent

Process for heat-treating a silicon wafer which includes the steps of contacting the surface of the silicon wafer with an aqueous solution containing hydrofluoric acid to remove metals from the wafer surface, contacting the hydrofluoric acid treated wafers with ozonated water to grow a hydrophilic oxide layer on the surface of the silicon wafer, and heating the ozonated water treated wafers to a temperature of at least about 300.degree. C. for a duration of at least about 1 second. The concentration of each of iron, chromium, calcium, titanium, cobalt, manganese, zinc and vanadium, on the surface of the silicon wafer at the initiation of the heating being less than 1.times.10.sup.9 atoms/cm.sup.2.

Pre-thermal treatment cleaning process

A process and a gettering agent for gettering metals from a solution. In the process, the solution is contacted with a gettering agent having a surface layer of SiO.sub.2, the layer of SiO.sub.2 preferably being greater than 15 angstroms in thickness.

Growing community of inventors

St. Peters, MO, United States of America

Larry W Shive