Adaptec, Inc.

Larry Tzu-Chiao Chen

Thomas Kennith Geiger

A computer implemented method for performing testing of a computer model of an integrated circuit design is disclosed. The method includes initially generating a first AVF test file for a first integrated circuit design having slow characteristics. Then, the method proceeds to generate a second AVF test file for a second integrated circuit design having fast characteristics. Once the two AVF test files are generated, the method proceeds to comparing test file parameters from the first AVF test file and the second AVF test file. Based on the comparisons, the method proceeds to generate a modified AVF test file that replaces miscompares (i.e., cycle slips) between output signals of the first and second AVF test files with don't care values. The method also includes options for performing pin margining. The pin margining operations are configured to make modifications to the AVF test files in order to compensate for expected physical test station adjustments.

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Hayward, CA, United States of America

Larry Tzu-Chiao Chen