Cisco Technology, Inc.

Scientific-atlanta, Inc.

Larry Stephen McKinney

Joel Warren Schoenblum

Kenneth W Heinrich

Leo Montreuil

Jiening Ao

Rezin E Pidgeon, Jr

William D Woodward

Joel Paul Jenkins

James Eugene Cannella, Jr

In one system embodiment, an overlapped block processing module configured to provide three-dimensional (3D) denoising of plural frames corresponding to a raw video sequence; and a frame alignment module configured to represent the raw video sequence with motion compensated frames corresponding to the raw video sequence, the motion compensated frames consisting of the plural frames and fewer in quantity than the quantity of frames of the raw video sequence, the plural frames based on prior temporally matched frames corresponding to the raw video sequence.

Processing prior temporally-matched frames in 3D-based video denoising

Summating temporally-matched frames in 3D-based video denoising

Consolidating prior temporally-matched frames in 3D-based video denoising

In one method embodiment, receiving a first temporal sequence of video frames, the first temporal sequence corrupted with noise; frame matching the video frames according to a first stage of processing; denoising the matched frames according to a second stage of processing, the second stage of processing commencing responsive to completion of the first stage of processing for all of the video frames, the second stage of processing comprising overlapped block processing; and wherein denoising further comprises accumulating denoised pixels for each iteration of the overlapped block processing in a two-dimensional (2D)+c accumulation buffer, the 2D accumulation buffer corresponding to the denoised pixels corresponding to a reference frame of the video frames, where c comprises an integer number of non-reference frame buffers greater than or equal to zero.

Efficient spatial and temporal transform-based video preprocessing

Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Switched phase and frequency detector based DPLL circuit with excellent wander and jitter performance and fast frequency acquisition

A broadband communications system uses modulation symbol transport over communications links to replace baseband or bandpass signal transport, thereby providing longer communication distances, lower communication link bandwidth, and greater signal quality. Subsequent to transporting the modulation symbols, the symbols are modulated and further transmitted over the RF transmission network.

Transport of modulation symbols in a communications system

An apparatus and method is disclosed which phase locks a frequency-agile modulated output signal to any selected channel of a comb generated output. The phase error of an input signal is tracked, the input signal is modulated up to a carrier output frequency, and the modulated output frequency is locked to the comb generator output by subtracting the input signal and negating the phase error.

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Hoschton, GA, United States of America

Larry Stephen McKinney