Seagate Technology Incorporated

Lsi Corporation

Larry Stephen King

Mark Ish

Horia Cristian Simionescu

Shashank Nemawarkar

William G Burroughs

Deepak Mital

Balakrishnan Sundararaman

Narender R Vangati

Steven J Pollock

Shailendra Aulakh

Te Khac Ma

In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Associative and atomic write-back caching system and method for storage subsystem

Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

Reducing data read latency in a network communications processor architecture

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Austin, TX, United States of America

Larry Stephen King