Hewlett-packard Company

Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Larry S Metz

Charles E Moore

Ulrich E Hess

Thomas M Walley

James R Hulings

Gordon W Motley

Duane A Fasen

Jerome E Beckmann

John H Stanback

Peter N Lim

Winthrop D Childers

Paul H McClelland

Kenneth E Trueba

Brian J Keefe

Steven Warren Steinfield

D Mitchel Hanks

Travis N Blalock

Rajeev Badyal

Richard A Baumgartner

Theodore G Rossin

Barbara Jean Duffner

Ran-Fun Chiu

Sui-hing Leung

Li Ching Tsai

Ronnie E Owens

Richard A Baugh

Robert A Zimmer

James S Ignowski

Kenneth R Stafford

George Rieck

Eldukar V Bhaskar

A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.

Method and apparatus for calibrating delay lines

Multi-phase clock time stamping for improving time stamp resolution is provided. One of many possible embodiments is a method for generating a time stamp having an improved time resolution for an event signal. Briefly described, one such method comprises the steps of: receiving an event signal for which a time stamp is to be generated; generating a first pulse signal having a pulse width defined by the event signal and a first clock signal; generating a second pulse signal having a pulse width defined by the event signal and a second clock signal; and determining which of the first pulse signal and the second pulse signal is to be used for generating the time stamp for the event signal.

Multi-phase clock time stamping

An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Analog implementation of a partial response maximum likelihood (PRML)

This invention provides an apparatus and method of fabrication thereof for an inkjet printhead with an improved ink flow path between an ink reservoir and vaporization chambers in an inkjet printhead. In the preferred embodiment, a barrier layer containing ink channels and vaporization chambers is located between a rectangular substrate and a nozzle member containing an array of orifices. The substrate contains two linear arrays of heater elements, and each orifice in the nozzle member is associated with a vaporization chamber and heater element. The ink channels in the barrier layer have ink entrances generally running along two opposite edges of the substrate so that ink flowing around the edges of the substrate gain access to the ink channels and to the vaporization chambers. The apparatus is fabricated without using ion implant technology.

Edge feed ink delivery thermal inkjet printhead structure and method of

An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.

Electrostatic discharge protection circuit for integrated circuits

A test system for a piezoelectric element per se or a piezoelectric element in a physical system, which is subject to forces which deform the piezoelectric element, couples an electrical pulse to the piezoelectric element sufficient to stress the element and induce mechanical ringing upon pulse removal. The ringing electrical signal developed by the piezoelectric element characterizes the functionality of the piezoelectric element. A response circuit which is responsive to the ringing electrical signal provides an electrical signal indicative of the functional condition of the piezoelectric element. The electrical signal is peak detected. The peak detected voltage is compared with a reference voltage to provide an indication of the functionality of the piezoelectric element.

Method and apparatus for testing a piezoelectric force sensor

A circuit for protecting integrated circuits from electrostatic discharge by using SCR latchup to divert the ESD current pulse away from sensitive circuit structures. The SCR structure of the invention includes a trigger circuit having an NMOS triggering transistor for activating the SCR when an ESD event occurs on an input/output pad of the integrated circuit being protected. The ESD event on the input/output pad of the integrated circuit is detected by a circuit which applies a trigger voltage to the NMOS triggering transistor to initiate latchup of the SCR independent of junction breakdown of the NMOS triggering transistor. The trigger voltage is generated by an inverter trigger or a capacitor trigger powered by the ESD event so as to trigger SCR latchup so long as the integrated circuit is not powered up (V.sub.DD is low). The SCR of the invention may also have a floating well whereby the well resistor R.sub.w of the SCR is replaced by a CMOS device which inhibits forward biasing of the pnp base of the SCR when V.sub.DD is high but allows small currents to forward bias the pnp base when V.sub.DD is low. The NMOS trigger FET of the invention also may be isolated from the substrate containing the SCR so as to further decrease the effects of junction breakdown conditions on the latchup of the SCR.

A fully-integrated CMOS peak detector stores the peak amplitude of an input signal using an on-chip storage capacitor. The fully-integrated CMOS peak detector includes a delay buffer, a transfer gate and a comparator. A discharge controller is used to step-down the peak amplitude stored on the on-chip storage capacitor some predetermined amount. The discharge controller includes a switched capacitor circuit which is placed in series with the storage capacitor such that the two capacitors act as a capacitive voltage divider to produce a predictable fraction of the acquired peak amplitude. Multiple peaks can be determined and/or stored by using multiple fully-integrated CMOS peak detectors in conjunction with a single comparator. A multiplexer is used in this configuration to control the multiple peak detectors.

CMOS peak amplitude detector

In a successive-approximation analog-to-digital conversion application, charge injection offset at the sample input of the comparator resulting from the changing DAC reference voltage, is converted to a fixed, systematic offset. In the comparator differential input stage, the reference or driven input device is turned off during a sample time, prior to beginning the conversion process, so that substantially all of a predetermined bias current flows in the sample side of the comparator. Given this initial condition, the change in input voltage through conversion is a fixed function of the device geometry, bias current and gain, independent of the sample voltage, and therefore may be calibrated out of the system. The comparator input stage includes a differential pair of MOS transistors. A CMOS transmission gate is coupled between the DAC output and the reference comparator input. A switch transistor is coupled between the reference input, i.e. the gate of M2, and Vdd for biasing off M2 during sample time. Transmission gate and switch transistor are controlled by a binary control signal 'sample/convert' to turn M2 off during a sample time, and to couple the DAC output to the reference input during convert time.

Successive approximation A/D converter correcting for charge injection

A latching CMOS comparator method and circuit are disclosed. The comparator circuit includes a differential input stage and a latching stage. The input stage includes a differential amplifier (MP3,MP4) and a Moore Mirror load. The load includes a first cross-coupled amplifier pair (MN3,MN4), and a pair of diode-connected transistors (MN1,MN2) coupled in parallel to the first amplifier to control gain. The input stage devices are sized to provide a gain on the order of 10 to 20. The latch clock signal (CLK) is isolated from the input stage to avoid injected charge offset error. The second or latching stage includes a second cross-coupled transistor amplifier (MP7,MP8) coupled to the input stage to provide additional gain. The latch clock signal is provided to a digital switch (MP9,MP10) which controls gain in the second amplifier. The digital switch enables a second pair of diode-connected transistors (MP5,MP6) disposed in parallel to the latch stage amplifier pair, to reduce gain during sampling, for a total input referenced gain on the order of 60 during sampling. The digital switch disables the diode-connected transistors during latching, so that the second amplifier operates at maximum gain during latching. The digital switch circuitry isolates the latch clock signal from the latching nodes. After latching, the diode-connected devices speed recovery by clamping the latching node voltages. The latching nodes are coupled through inverters to an RS flip-flop circuit.

CMOS latching comparator

An improved thermal inkjet printhead having MOSFET drive transistors incorporated therein. The gate of each MOSFET transistor is formed by applying a layer of silicon dioxide onto a silicon substrate, applying a layer of silicon nitride onto the silicon dioxide, and applying a layer of polycrystalline silicon onto the silicon nitride. Portions of the substrate surrounding the gate are oxidized, forming field oxide regions. Drain and source regions are then conventionally formed, followed by the application of a protective dielectric layer onto the field oxide, drain, source, and gate. A resistive layer is deposited on the dielectric layer and directly connected to the source, drain, and gate. A conductive layer is deposited on a portion of the resistive layer, ultimately forming both covered and uncovered regions thereof. The uncovered region functions as a heating resistor, and the covered regions function as electrical contacts to the transistor and resistor.

Thermal inkjet printhead structure and method for making the same

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Fort Collins, CO, United States of America

Larry S Metz