Nvidia Corporation

Mellanox Technologies, Ltd.

U.S. Department of Energy

Larry Robert Dennison

Nan Jiang

Benjamin Klenk

William James Dally

Joel S Emer

Stephen William Keckler

Angshuman Parashar

Mark Douglas Hummel

Gregory Michael Thorson

Hans Eberle

Samuel Hammond Duncan

Matthias Augustin Blumrich

Olivier Giroux

Glenn A Dearth

Sanjeev Jain

Vyas Venkataraman

Hemayet Hossain

Alexander Toichi Ishii

Nir Haim Arad

Noam Bloch

Gil Bloch

Daniel Marcovitch

Lion Levi

Alan Lynn Davis

Richard Leigh Graham

Dane Mrazek

Aviad Levy

Karan Gupta

John Martin Snyder

Eric Anderson

A method is provided for operating a network switch comprising a plurality of input ports and a plurality of output ports. The method comprises receiving a first data packet received via a first input port and a second data packet received via a second input port to be delivered to an egress endpoint connected to a first output port, configuring a plurality of crossbar switch units arranged in a tiled architecture to pass the first data packet to the first output port via a primary path and pass the second data packet to the first output port via a secondary path, and transmitting the first data packet and the second data packet to the egress endpoint. The first data packet and the second data packet pass through the plurality of crossbar switch units simultaneously.

Crossbar multipathing for multicast performance in tiled switches

Aggregation of small payloads from multiple packets may improve bandwidth efficiency of a network, particularly a high-performance compute cluster with thousands of network endpoints and distributed data. Aggregation is context-based and a packet header is reduced because the common components that are shared by the aggregated messages are included once within the header. Execution contexts are explicitly created and destroyed by application programs. Each participating endpoint stores context-specific properties until the context is destroyed, so that the properties are not included in the header. Aggregation may be performed at different hierarchical levels by switches and/or endpoints.

In-network message aggregation for efficient small message transport

A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.

Sparse convolutional neural network accelerator

A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

Use of stashing buffers to improve the efficiency of crossbar switches

Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.

Transceiver system with end-to-end reliability and ordering protocols

An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

Small message aggregation

A network device configured to perform scalable, in-network computations is described. The network device is configured to process pull requests and/or push requests from a plurality of endpoints connected to the network. A collective communication primitive from a particular endpoint can be received at a network device. The collective communication primitive is associated with a multicast region of a shared global address space and is mapped to a plurality of participating endpoints. The network device is configured to perform an in-network computation based on information received from the participating endpoints before forwarding a response to the collective communication primitive back to one or more of the participating endpoints. An injection policy comprising the issuing of credits enables each endpoint to limit the amount of collective communication primitives injected into the network simultaneously to reduce network congestion caused by increased network traffic due to the multicast capability of the network devices.

Injection limiting and wave synchronization for scalable in-network computation

A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Scalable light-weight protocols for wire-speed packet ordering

A network device configured to perform scalable, in-network computations is described. The network device is configured to process pull requests and/or push requests from a plurality of endpoints connected to the network. A collective communication primitive from a particular endpoint can be received at a network device. The collective communication primitive is associated with a multicast region of a shared global address space and is mapped to a plurality of participating endpoints. The network device is configured to perform an in-network computation based on information received from the participating endpoints before forwarding a response to the collective communication primitive back to one or more of the participating endpoints. The endpoints can inject pull requests (e.g., load commands) and/or push requests (e.g., store commands) into the network. A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device.

Scalable in-network computation for massively-parallel shared-memory processors

A technique for performing data parallel training of a neural network model is disclosed that incorporates batch normalization techniques using partial populations to generate normalization parameters. The technique involves processing, by each processor of a plurality of processors in parallel, a first portion of a sub-batch of training samples allocated to the processor to generate activations for the first portion of the sub-batch. Each processor analyzes the activations and transmits statistical measures for the first portion to an additional processor that reduces the statistical measures from multiple processors to generate normalization parameters for a partial population of the training samples that includes the first portion from each of the plurality of processors. The normalization parameters are then transmitted back to each of the processors to normalize the activations for both the first portion and a second portion of the sub-batch of training samples allocated to each processor.

Distributed batch normalization using partial populations

Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Securing memory accesses in a virtualized environment

A technique utilizing speculative execution and rollback for performing data parallel training of a neural network model is disclosed. Activations for a layer of the neural network model are normalized during a speculative normalization operation using estimated normalization parameters associated with a partial population of a set of training data allocated to a particular processor. Normalization parameters associated with the total population of the set of training data are generated by a distributed reduce operation in parallel with the speculative normalization operation. An optional rollback operation can revert the activations to a pre-normalization state if the estimated normalization parameters for the partial population are subsequently determined to be inaccurate compared to the normalization parameters for the population of the set of training data distributed across a plurality of processors.

Growing community of inventors

Mendon, MA, United States of America

Larry Robert Dennison