Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Lucent Technology

Larry R Tate

Sivanand Simanapalli

Mark Ernest Thierbach

Mazhar M Alidina

Mohammad Shafiul Mobin

Douglas J Rhodes

Carl R Holmqvist

A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.

Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits

A novel table look-up/indirect addressing system and method uses a dual fetch Harvard architecture to accomplish one full table look-up access per instruction cycle. The offset access fetch, the indirect data fetch and the table offset and base address addition are all performed during a single cycle. The system and method also accommodate data accesses using packed (half word) offsets.

System and method for performing table look-ups using a multiple data fetch architecture

A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, high and low parts. The method and apparatus enable vectoring the respective first and second high parts from the accumulators to define a single vectored register responsive to a single instruction cycle and processing the data in the vectored register.

Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture

The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit and a multiplexer. The value from the group and the predetermined value are compared in the arithmetic logic unit. A selector is set to one of a first or second logic state. In the first logic state the selector selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag set by the comparison in the arithmetic logic unit and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to a first state and the value is less than the predetermined value. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to the second state and the value is greater than the predetermined value.

Single-cycle accelerator for extremun state search

A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer causes a two cycle non-interruptable instruction to be initiated. The first cycle is a 16-bit misaligned data fetch. The address pointer is incremented by 2 and stored in a temporary pointer register. The second cycle is a 32-bit double word fetch based on the temporary pointer with its least significant bit set to 0 (an aligned fetch). The low word from this fetch is used to satisfy the current misaligned double word fetch and the high word is stored in a temporary buffer register in case it proves useful in subsequent misaligned double fetch instructions. Finally, the temporary address pointer is incremented by 2 for possible use in subsequent misaligned fetches. If a subsequent misaligned fetch using the same address pointer is detected, a one-cycle misaligned double word fetch may be simulated by using the buffered memory fetch data combined with another aligned double word fetch and an appropriate pointer update. A double word per cycle data rate may thereby be maintained during an entire sequence of misaligned data fetches, except when processing the first state of the loop, during which time the buffer is set up.

Non-aligned double word fetch buffer

A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer. The control circuit provides the output of the adder to the address pointer latch as an updated address pointer when the indicators take on predetermined values and the comparator output is in the second state. The control circuit provides the beginning address to the address pointer latch as an updated address pointer when the indicators take on predetermined values and the comparator output is in the first state. An advanced address pointer may be used to enhance performance in misaligned memory accesses.

Modulo address generator for generating an updated address

In accordance with the invention, a method of generating a soft symbol confidence level for use in decoding a received digital signal includes calculating a difference between two potential next state accumulated costs to provide a soft symbol confidence level. Simultaneously with calculating the difference between two potential next state accumulated costs, performing a compare-select operation to identify one of the two potential next state accumulated costs as an extremum of the two present state accumulated costs.

Single-cycle, soft decision, compare-select operation using dual-add

There is disclosed, a method and apparatus for processing a signal in a pipeline. The method includes retrieving a present state cost. Simultaneously with receiving the present state cost, an estimated symbol and a received symbol are obtained, a difference between the received and estimated symbols is found, the difference between the received and esitmated symbols is squared, and the present state cost is added to the squared difference to generate a next state cost. The apparatus includes hardware to carry out the method.

Metric acceleration on dual MAC processor

There is disclosed a first adder subtractor combines the largest positive number or largest negative number capable of being represented by the number of bits in the datapath, as determined by the sign of an input to a second adder with a first input to generate a first potential sum. A second adder operating in parallel with the first adder combines first, second and third inputs to generate a second potential sum. An overflow detector combines the first and second inputs of the second adder to determine if there is an overflow. If an overflow is not present, a multiplexer selects the output of the second adder as the output to be saturated. If an overflow is present, the multiplexer selects the output from the first adder as the output to be saturated.

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South Barrington, IL, United States of America

Larry R Tate