Lattice Semiconductor Corporation

Cypress Semiconductor Corporation

Larry R Metzger

Om P Agrawal

Kerry A Ilgenstein

Claudia A Stanley

Xiaojie (Warren) He

Chong M Lee

Robert A Simon

Sunil D Mehta

Michael P Taborn

Robert M Balzli, Jr

David R Horton

In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be electrically isolated from an input to the bent-gate input stage transistor by forming at least one bent-gate grounded-gate transistor between the bent-gate output stage transistor and the input to the bent-gate input stage transistor.

Circuit layout for improved performance while preserving or improving density

An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g., &lE;5 PT's) to having slower generation of sums of a much larger number of PT's (e.g., &lE;160 PT's).

Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures

An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.

Scalable architecture for high density CPLD's having two-level hierarchy of routing resources

Scalable architecture for high density CPLDS having two-level hierarchy of routing resources

An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.

Enhanced macrocell module for high density CPLD architectures

A multi-featured first-in-first-out (FIFO) memory device on a monolithic semiconductor integrated circuit chip. The FIFO device is bi-directional, in that the user may select the direction of data transfer through the device. The device may be configured in a transparent bypass mode of operation, wherein the FIFO memory array is bypassed, and data is transferred directed from either device input/output port to the other device input/output port. In another mode of operation allowing registered bypass operation, a byte of data may be written in an internal register from the device port being used to output data for later transfer to the device port presently being used to input data to the FIFO memory array. The FIFO device further includes a user-testable mode of operation, wherein data written into the FIFO memory array through a device input port may be read out of the same device input port. Device mode selection occurs through control pin slew detection, allowing mode selection with a minimum number of control pins.

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Austin, TX, United States of America

Larry R Metzger