Avici Systems, Inc.

Future Wei Technologies, Inc.

Extreme Networks, Inc.

General Computer Corporation

Larry R Dennison

William James Dally

Philip P Carvey

William Frederick Mann, Iii

P Allen King

Gregory M Waters

Derek Chiou

Paul A Beliveau

Steven E Golson

A Provider Network Controller (PNC) addresses the challenges in building services across Next Generation Network (NGN) architectures and creates an abstraction layer as a bridge, or glue, between the network transport and applications running over it. The PNC is a multi-layer, multi-vendor dynamic control plane that implements service activation and Layer 0-2 management tools for multiple transport technologies including Carrier Ethernet, Provider Backbone Transport (PBT), Multi-protocol Label Switching (MPLS), Transport MPLS (T-MPLS), optical and integrated networking platforms. Decoupling transport controls and services from the network equipment simplifies service creation and provides options for carriers to choose best-in-class equipment that leverages the PNC to enable rapid creation and management of transports and services. The PNC provides Service-Oriented Architecture (SOA) interfaces to abstract transport objects expressly designed to support both wholesale and retail services, and supports service offerings with varied bandwidth and Quality of Service (QoS) requirements, thus achieving enterprise Ethernet economics.

Software control plane for switches and routers

An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links. A virtual channel is enabled for possible assignment to an output fabric link upon receipt of an indication that an input buffer is available at the next fabric router of the path.

Internet switch router

Sort elements, such as queues processed in a network processor, are provided with relative priorities relative to each other. A set of relative priorities is used to specify priority order of the sort elements. The priority order may be specified by addressing code in a jump table. Duplicate code in the jump table having multiple entrance points allows for reduction of the size of the jump table. The relative priorities may be applied to a lookup table, hash or other function in order to address the jump table.

Priority sorting

An Internet router treats plural output ports with a common destination as a composite port. A routing table uses the IP address to determine a composite trunk to which the packet is to be forwarded. A forwarding table identifies a route along a routing fabric within the router to a specific output port of the composite port. Output ports and fabric routes are selected to maintain order within a flow by routing the flow along a single fabric route to a single output trunk. The forwarding table may favor output ports which are nearest to a packet input port, and the forwarding table may be modified to dynamically balance load across the trunks of a composite trunk.

Composite trunking

A processor, particularly a network processor, is designed by first writing code to be processed by the processor. That code is then electronically compiled to design hardware of the processor and to provide executable code for execution on the designed hardware. To facilitate compilation, the written code may be restricted by predefined functional units to be implemented in hardware, and the executable code may include very long instruction word code. The functional units may be implemented in reconfigurable circuitry or custom circuitry, and the designed hardware may include combinational logic in reconfigurable circuitry.

Compilable, reconfigurable network processor

In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent winners in comparisons of scheduling values of sibling nodes of the tree structure. CBR scheduling values may first be compared to select a queue and, if transmission from a CBR queue is not timely, a packet may be selected using WFQ scheduling values. The scheduling values are updated to reflect variable packet lengths and byte stuffing in the prior packet. Scheduling may be performed in multiple stages.

Apparatus and method for packet scheduling

Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

Prefix search circuitry and method

In scheduling a packet, latency requirements of the packet is determined. The packet is then scheduled according to its latency requirements. Queues may be assigned latency ranges and packets are assigned to the queues according to those ranges. Within ranges, queues of different priorities may be provided.

Latency-based scheduling and dropping

Prefix search method

A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set. Each configuration controller operates as a remotely configurable switch that configures a topology formed by the backplanes and the module connectors. In particular, by adding a single module, the topology can be expanded incrementally.

Apparatus and methods for connecting modules using remote switching

The required length of a route descriptor in a source routing system is obtained by inserting an implied exit field, use of run-length encoding, and use of variable-length encoding. In the variable-length encoding, codes having lesser bits are reserved for preferred directions. Preferred direction may be encoded in the routing header, and it may be implied by the arrival port.

Space-efficient source routing

A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the data packets. The router further includes control circuitry, coupled with the input and output physical channels and the data buffers, for generating virtual channel assignments that assign virtual channels to the data packets, and generating physical channel assignments that assign the output physical channels to the virtual channels. Each of the assignments is generated in response to queued arrival and credit events. The portions of the data packets are forwarded from the data buffers to the output physical channels according to the generate virtual and physical channel assignments.

Growing community of inventors

Norwood, MA, United States of America

Larry R Dennison