Matsushita Electric Corporation of America

Matsushita Electric Industrial Co., Ltd.

Larry Phillips

Saiprasad V Naimpally

Edwin Robert Meyer

Hee-Yong Kim

Shuji Inoue

Richard Sita

Robert T Ryan

Ren Egawa

Ghanshyam Dave

Michael Iaquinto

Jereld Pearson

Edward Brosz

Kurt Dustin

Ric Conover

Robert Meyer

A video data storage system holds MPEG compressed video data on a hard disk drive. A transport decoder receives a bit-stream including the compressed audio and video data formatted as transport packets and that reformats the compressed audio and video data into respective program elementary stream (PES) packets. The system stores the audio and video PES packets onto a disk. The system also includes separate audio and video buffer memories that hold the audio and video PES packets when they are read from the disk drive. An MPEG decoder separately accesses the audio and video data from the respective audio and video buffer memories. The audio buffer memory has an amount of memory sufficient to provide the MPEG decoder with audio data representing ten seconds of decoded audio signal. In one embodiment, when a soft error occurs, the MPEG decoder continues to read and decode data from the audio buffer, but stops reading and decoding data from the video buffer. During this time, the MPEG decoder continually displays a current image. After the disk has recovered from the soft error, the MPEG decoder continues to retrieve and decode video data from the video buffer memory and drops P or B frames to resynchronize the video data stream to the audio data stream.

Method and apparatus for concealing disk soft errors in recorded digital television signals

A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which decodes an ATSC encoded image and employs a downconversion process to produce a standard definition video signal. The video decoder includes a frequency-domain filter to reduce the resolution of the ATSC encoded signal. The video decoder downconversion system also includes a formatting section having vertical and horizontal filters, as well as resampling processing, to format the decoded and downconverted video image for a particular display and aspect ratio. The decoder senses the display format of the encoded video signal and changes the processing provided by the decoder to produce a standard definition output signal regardless of the display format of the encoded input signal. The system also includes a format converter which may be programmed to use a plurality of methods to convert the aspect ratio of the input signal for display on a display device having a different aspect ratio. In one mode, the system sequences through the possible methods to allow the user to select one method.

HDTV downconversion system

An HDTV down conversion system including apparatus for forming a set of low resolution down-sampled pixel values corresponding to a current frame of a video signal from a set of low resolution pixel values corresponding to a residual image of a current frame of the video signal and from a set of down-sampled low resolution pixel values corresponding to reference frames of the video signal. The apparatus includes a memory for storing the set of down-sampled low resolution pixel values. An up-sampling processor receives from the memory and uses Lagrangian interpolation to convert the set of down-sampled low resolution pixel values corresponding to the reference frame of the video signal into a set of up-sampled low resolution pixel values corresponding to the reference frame of the video signal. A summing processor adds the set of low resolution pixel values corresponding to the residual image of the current frame of the video signal to the set of up-sampled low resolution pixel values corresponding to the reference frame of the video signal to form a set of low resolution pixel values corresponding to the current frame of the video signal. A decimating processor deletes selected ones of the set of low resolution pixel values corresponding to the current frame to generate the set of low resolution down-sampled pixel values corresponding to the current frame of the video signal.

Upsampling filter for a down conversion system

A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which, when the decoder is operated in a first mode, decodes a Main Profile, High Level (MP&commat;HL) image to produce a high-definition video output signal and decodes a Main Profile, Main Level (MP&commat;ML) signal to produce a standard definition video signal. In addition, when the decoder is operated in a second mode, circuitry is used which generates a standard definition image from the MP&commat;HL signal. The video decoder includes a frequency-domain filter to reduce the resolution of the MP&commat;HL signal when the decoder is operated in the second mode.

MPEG decoder providing multiple standard output signals

An HDTV down conversion system including an apparatus for forming a low resolution 2:1 down converted video signal from an encoded video signal representing a video image. The encoded video signal is a frequency-domain transformed high resolution video signal with motion prediction. The apparatus includes a receiver for receiving encoded video signals as a plurality of high resolution frequency-domain video coefficient values. A down conversion filter receives and weights the high resolution frequency-domain video coefficient values to form a set of low passed frequency-domain video coefficients. An inverse-transform processor transforms the set of frequency-domain video coefficients into a set of pixel values. An averaging filter transforms selected ones of the pixel values in the set of pixel values into averaged pixel values. A decimating processor deletes selected ones of the set of pixel values to provide the low resolution video signal.

Efficient down conversion system for 2:1 decimation

An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and off processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform.

Inverse discrete cosine transform processor using parallel processing

An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and odd processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform. The 1-D IDCT processors each include input section circuits which each receive four-bits of 12-bit or 16-bit input values and provides one bit of each of four input values in a four clock cycle time period. Each of the 1-D IDCT processors also includes an accumulator section which includes adders which sum M-1 bit values to produce an M-bit output value. Any bits of less significance than the M-1 input values are applied to carry logic circuitry which generates a carry signal without generating a sum signal for these less significant bits. The carry is combined with output value produced by each accumulator section.

Inverse discrete cosine transform processor having optimum input

Carry logic that produces a carry value from NLSBs for a ROM accumulator

A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value. The count value is compared to a succession of externally supplied system clock reference (SCR) values to generate a phase difference signal that is used to adjust the frequency of the signal produced by the DPLL. In addition, the DPLL is aligned in phase by substituting respective portions of the SCR value for the count value developed by the DPLL and for the accumulated phase value used by the DPLL.

MPEG video decoder having a high bandwidth memory

A parallel decoder for an MPEG-2 encoded video signal includes a deformatter which separates the input bit stream into multiple portions, each representing a respectively different section of the HDTV image. The separate portions are processed in parallel by respective decoders. In order to perform motion compensated processing, each of the four decoders includes a memory that holds data representing the entire image. Each decoder provides its decoded output data to all of the decoders to maintain the data in the respective memories.

Parallel architecture for a high definition television video decoder

A system and method for filtering a digital signal having a relatively high data rate uses circuitry which operates at a lower data rate. The filter includes an input section which receives the input signal and which divides the input signal into a plurality of contiguous segments. The system also includes a first filter which receives samples representing one of the plurality of segments and adjacent samples from the next contiguous one of the segments and which filters all of the received samples to produce a first filtered signal. A second filter receives samples of the next contiguous segment and filters those samples to produce a second filtered signal. The filtered signals are combined by providing the samples of the second filtered signal immediately after the samples of the first filtered signal to produce a filtered output signal. The invention also relates to using respective timing signals associated with the segments to determine when the samples of the first and second filtered signals are provided.

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Collingswood, NJ, United States of America

Larry Phillips