Intel Corporation

Larry O Smith

Gilbert A Neiger

Richard A Uhlig

Glenn J Hinton

Rajesh M Sankaran

Dion Rodgers

Andrew V Anderson

Steven M Bennett

Rajesh Sankaran Madukkarumukumana

Scott Dion Rodgers

Martin Guy Dixon

Hong Wang

Andrew F Glew

Per H Hammarlund

Raj K Ramanujan

Ittai Anati

Konrad K Lai

John Thomas Shen

Erik C Cota-Robles

James B Crossland

Darrell D Boggs

David A Koufaty

Bryant E Bigbee

David Zimmerman

Xiang Chris Zou

Robert S Chappell

Stalinselvaraj Jeyasingh

James Paul Held

Scott H Robinson

Anil Aggarwal

Doron Orenstein

Michael A Kozuch

Rupin H Vakharwala

Rajesh S Parthasarathy

Alain Kagi

Chris J Newburn

Sham M Datta

Camron B Rust

Muthukumar Swaminathan

Adrian C Moga

Sunil R Shenoy

Wayne Alan Downer

Madhavan Parthasarathy

Erich Boleyn

Steve M Bennett

Scott B Huck

Scott J Cape

Shivanandan Kaushik

Bill Alexander

Andrew Anderson

Roger Dion

Wayne A Downer

In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Apparatus, method, and system for implementing micro page tables

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses

Translating a guest virtual address to a host physical address as guest software executes on a virtual machine

In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

Apparatus and method for directing micro architectural memory region accesses

Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system

Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

Programmable event driven yield mechanism which may activate service threads

A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.

Virtualizing memory type

Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.

Methods and systems to control virtual machines

An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit. Several different time critical code sections may be loaded and locked into the cache at different times.

Apparatus and method for an instruction cache locking scheme

Growing community of inventors

Beaverton, OR, United States of America

Larry O Smith