Intel Corporation

Larry M Mennemeier

Alexander D Peleg

Benny Eitan

Millind Mittal

Carole Dulong

Eiichi Kowashi

Yaakov Yaari

Wolf C Witt

Derrick Chu Lin

David Bistry

Stephen Anthony Fischer

Punit Minocha

Andrew F Glew

Srinivas Chennupaty

Romamohan R Vakkalagadda

Tuan H Bui

Derrik Lin

Ramamohan R Vakkalagadda

Benny Maytal

Mohammad A Abdallah

William W Macy, Jr

Eric L Debes

Doron Orenstein

Michael A Julier

Robert S Dreyer

Koby Gottlieb

Jonathan Jay Tyler

Ticky Thakkar

Ofri Wechsler

Milland Mittal

Katherine Kong

Mike S Kelly

Coby Gottlieb

David I-Keong Wong

Ahmet Bindal

Yaacov Yaari

An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Orderly storing of corresponding packed bytes from first and second source registers in result register

A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the third register as a destination register. And to decode a pack instruction to identify a fourth and a fifth register each having 16-bit data elements. At least one functional unit, responsive to the packed instruction, to store a result in the third register including only half of all data elements of each of the first and second registers, including only corresponding data elements from corresponding positions in the first and second registers, and responsive to the pack instruction to store a result that is to include an 8-bit data element for each 16-bit data element in the fourth and fifth registers.

Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

Interleaving half of packed data elements of size specified in instruction and stored in two source registers

A processor of an aspect includes a register file including a first register to hold a first packed data including a first low data element and a first high data element, a second register to hold a second packed data including a second low data element and a second high data element, and a third register. The processor also includes a decoder to decode an unpack instruction. The processor also includes a functional unit coupled with the decoder and the register file. The functional unit, in response to the decoder decoding the unpack instruction, is to transfer the first low data element to a high position of the third register and the second low data element to a low position of the third register.

Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers

Processor executing unpack and pack instructions specifying two source packed data operands and saturation

Packing in destination register half of each element with saturation from two source packed data registers

Packing odd bytes from two source registers of packed data

Packing lower half bits of signed data elements in two source registers in a destination register with saturation

Method and apparatus for unpacking and moving packed data

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Processor for performing multiply-add operations on packed data

Packing signed word elements from two source registers to saturated signed byte elements in destination register

Method and apparatus for performing multiply-add operations on packed data

Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register

Growing community of inventors

Boulder Creek, CA, United States of America

Larry M Mennemeier