Advanced Micro Devices Corporation

Paypal, Inc.

Synopsys, Inc.

Maxim Integrated Products, Inc.

Larry Lingjer Wang

Nick Kepler

Christopher F Lyons

Olov B Karlsson

Effiong Etukudo Ibok

Basab Bandyopadhyay

Paul Raymond Besser

Karsten Wieczorek

Kevin Ward

Vijeyta Aggarwal

Mayank Chaudhary

Nischitha Thimmappa Gowda Sundaramma

Alexander Kalnitsky

Albert M Bergemont

Andrew Edward Horch

Harry Luan

Yi He

Wei Zhao

Charlie Cheng

Sang Hoon Park

Viktor Zekeriya

Tao Su

Oleg Ivanov

Sean Lynch

Che-Ping Chen

Chun Jian

Basab Bandyopadhyah

Effiong Obok

Basab Bandyophadhyay

Various systems, mediums, and methods may involve a provider application configured to access a user account associated with a provider server. For example, a system may perform operations to identify one or more other applications installed on the mobile device that may be configured to communicate with the provider server. The system may determine data required by the other applications to perform one or more data transfers with the user account. The system may cause the provider application to send the data required to the other applications. As such, the other applications may be enabled to perform one or more data transfers with the user account based on the data sent to the other applications.

Mobile application configurations to enable data transfers

A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M−1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further includes, in part, M×N anti-fuses. Each anti-fuse is associated and forms a bitcell with a corresponding one of the M×N select transistors.

One time programmable bitcell with select device in isolated well

Systems and methods for managing user data across multiple apps are disclosed. An example method includes, determining that an installation of a first app on a user device is completed; identifying a second app in which a user has been authenticated and has been installed on the user device; obtaining a second set of user information associated with the user from the second app; and configuring a user account of the user in the first app using the second set of user information. In some implementations, identifying the second app is executed in response to determining that the installation of the first app on the user device is completed. In some other implementations, identifying the second app is executed in response to a user selection of the first app after the installation.

User data management across multiple apps on a user device

Gate oxide breakdown in the programming element of an OTP (One-Time Programmable) memory cell can vary widely. The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array is described.

Gate oxide breakdown in OTP memory cells for physical unclonable function (PUF) security

An integrated circuit OTP memory cell has a programming element with enhanced programmability. The programming element has a doped region at the surface of a semiconductor substrate and a conducting layer partially extending over a surface of the semiconductor surface and along a boundary of the doped region. The conducting layer is displaced from the surface of the doped region and the semiconductor substrate by a thin oxide layer. The partially extending conducting layer provides locations to concentrate electric fields and rupture the gate oxide layer during programming.

OTP cell with improved programmability

An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

Three-transistor OTP memory cell

A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.

Dynamic trim method for non-volatile memory products

A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited using high density plasma (HDP) techniques, is deposited over an extrinsic base layer and over a sacrificial emitter structure. Because of the particular characteristic of the HDP oxide, the deposition of HDP oxide forms a triangular-like structure over the sacrificial emitter structure having a maximum thickness less than the thickness of the HDP oxide over the extrinsic base layer. This facilitates the complete removal of the HDP oxide above the sacrificial emitter layer without the complete removal of the HDP oxide above the extrinsic base layer. This allows the removal of the sacrificial emitter structure while the remaining HDP oxide, serving as a mask, protects the underlying extrinsic base layer.

Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT

An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

Shallow trench isolation formation with ion implantation

High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.

Prevention of dopant out-diffusion during silicidation and junction formation

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San Jose, CA, United States of America

Larry Lingjer Wang