D2s, Inc.

Infineon Technologies Ag

Larry Lam Chau

Tam Dinh Thanh Nguyen

Akira Fujimura

Kenji Yoshida

Takashi Mitsuhashi

Shohei Matsushita

Donald Benton MacMillen

Trang Pham

Helena H Nguyen

An integrated circuit comprising a plurality of standard cell circuit elements is disclosed, wherein for at least one layer of the integrated circuit, a majority of minimum-width patterns are in a preferred diagonal orientation.

Integrated circuit designed and manufactured using diagonal minimum-width patterns

Methods for designing and manufacturing an integrated circuit are disclosed, in which the physical design process for a standard cell or cells utilizes a preferred diagonal direction for minimum-width patterns on at least one layer, where the standard cell or cells are used in the layout of an integrated circuit. The methods also include forming the patterns on a photomask using model-based fracturing techniques with charged particle beam simulation, and forming the patterns on a substrate such a silicon wafer using the photomask and an optical lithographic process with directional illumination which is optimized for the preferred diagonal direction.

Method for integrated circuit design and manufacture using diagonal minimum-width patterns

The present invention increases the number of characters available on a stencil for charged particle beam lithography. A stencil for charged particle beam lithography is disclosed, comprising two character projection (CP) characters, wherein the blanking areas for the two CP characters overlap. A stencil is also disclosed comprising two CP characters with one or more optional characters between the two characters, wherein the optional characters can form meaningful patterns on a surface only in combination with one of the two characters. A stencil is also disclosed wherein the blanking area of a CP character extends beyond the boundary of the stencil's available character area. Methods for design of the aforementioned stencils are also disclosed.

Cell projection charged particle beam lithography

A 7-track standard cell library having a layout architecture that is designed for fabrication technologies having design rules of 0.12 microns or smaller. The cells are laid out using a routing grid having horizontal and vertical grid spacings of 0.4 microns, such that the height of each 7-track standard cell is 2.8 microns (i.e., seven track spacings based on a horizontal grid spacing of 0.4 microns). Power rails are implemented using M1 structures. The seven-track cell height is divided into four tracks on the P-side and three tracks on the N-side. Complex cells include one internal connection line (structure) formed using the third metal layer (M3) that is introduced in a predetermined track (e.g., the second track from the top of the cell) to facilitate the seven-track layout.

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Fremont, CA, United States of America

Larry Lam Chau