Texas Instruments Corporation

Other

Teknekron Infoswitch Corporation

Yt Networks Capital, LLC

Yotta Networks, Inc.

Larry L Miles

Lakshman S Tamil

Gregory H Aicklen

Scott A Rothrock

Nolan J Posey, Jr

Stephen P Hamilton

Charles P Grant, Jr, Deceased

John D Meyers

Thomas E Merrow

Noland J Posey, Jr

A router, comprising: a core controller; a plurality of egress edge units coupled to said core controller, said plurality of egress edge units including at least one egress port; and a plurality of ingress edge units coupled to said core controller and in communication with said plurality of egress edge units, wherein each ingress edge unit comprises: a plurality of ingress ports; an ingress interface associated with each ingress port, each ingress interface operable to segregate incoming optical data into a plurality of subflows, wherein each subflow contains data intended for a particular destination port; and a TWDM multiplexer operable to: receive subflows; generate a micro lambda from each subflow; time multiplex each micro lambda according to a schedule pattern; wavelength multiplex each micro lambda; and transmit each micro lambda to a switch fabric according to the schedule pattern.

Port-to-port, non-blocking, scalable optical router architecture and method for routing optical traffic

One embodiment of the present invention includes a router comprising an ingress edge unit with one or more ports and an egress edge unit with one or more ports connected by a switch fabric. The ingress edge unit can receive optical data and convert the optical data into a plurality of micro lambdas. The ingress edge unit can convert the incoming data to micro lambdas by generating a series of short-term parallel data bursts across multiple wavelengths. The ingress edge unit can also wavelength division multiplex and time domain multiplex each micro lambda for transmission to the switch fabric in a particular order. The switch fabric can receive the plurality of micro lambdas and route the plurality of micro lambdas to the plurality of egress edge units in a non-blocking manner.

A system and method for providing non-blocking routing of optical data through a telecommunications router that allows full utilization of available capacity. The router includes a number of data links that carry optical data packets to and from an optical router. The optical router includes a number of ingress edge units coupled to an optical switch core coupled further to a number of egress edge units. The ingress edge units receive the optical data packets from the data links and aggregate the optical data packets into &ldquo;super packets&rdquo; where each super packet is to be routed to a particular destination egress edge unit. The super packets are sent from the ingress edge units to an optical switch fabric within the optical switch core that routes each super packet through the optical switch fabric to the super packet's particular destination egress edge unit in a non-blocking manner (i.e., without contention or data loss through the optical switch fabric). This routing is managed by a core controller that monitors flow information at each ingress edge unit to control the super packet generation and transmission to the optical switch fabric and schedules each super packet to exit the optical switch fabric so as to avoid contention among the plurality of super packets in the transmission between the optical switch fabric and the egress edge units. The egress edge units receive the super packets, de-aggregate the super packets into the original optical data packets, and transmit the optical data packets to the data lines.

Non-blocking, scalable optical router architecture and method for routing optical traffic

A time slot interchange switch matrix incorporates processor-controlled diagnostic functions to provide programmable on-line/off-line diagnostic monitoring. The switch matrix output can be tri-stated during program-selected time slots while remaining electrically connected to the PCM buses, allowing redundant switch matrices to share on-line time slot interchange switching in any programmable manner. Inject and monitor circuitry enables the switching function of the on-line switch matrix to be tested time slot by time slot under program control using unused time slots. Parity checking, including verification of check circuitry, is provided for input PCM data, control memory addressing output, and data memory output through the tri-state output drivers. In addition to on-line inject and monitor testing, the off-line switch matrix selectively monitors the output of the on-line matrix to confirm that it is driving the PCM buses. If a malfunction is detected, the faulty switch matrix may be electrically disconnected from PCM buses by remote command.

Digital information switch matrix with on-line/off-line diagnostic

A method and system for driving a liquid crystal display (LCD) with adjustable drive voltages to match selected ones of a number of different liquid crystal materials utilize variable duty cycle control. Instead of regulating the battery supply voltage to provide desired driving voltage, the driving voltage is disabled for preselected portions of each cycle thereby controlling the root mean square voltage across the LCD segments during both the display-on and display-off states of each display segment to match the liquid crystal material. Two-, three- and four-way multiplexing or any other level of multiplexing may be used in conjunction with this method and system.

RMS Voltage control with variable duty cycle for matching different

RMS voltage control with variable duty cycle for matching different

An electronic calculator or microprocessor system is provided with a semiconductor chip having a prechargeable and conditionally dischargeable instruction word memory, a program counter for addressing the instruction word memory, and a power up clear circuit. The power up clear circuit includes a latch circuit having two states, the first state being preferentially entered on when electrical power is first provided to the latch circuit and a second state which is entered at some time thereafter, and a gating circuit for interrupting the addressing of the instruction word memory by the program counter when said latch circuit is in the first state.

Power up clear system for an electronic calculator or microprocessor

An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a arithmetic unit and memory system. The arithmetic unit and memory system include a plurality of operational registers and an arithmetic unit having two inputs and an output. A plurality of operational registers selector gates interconnect the operational registers and arithmetic unit for connecting any selected two of the plurality of operational registers to the inputs of the arithmetic unit. The plurality of operation register selector gates preferably comprise individual MOS transfer gates.

Electronic calculator or microprocessor having a multi-input arithmetic

An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having an arithmetic unit for performing arithmetic operations on the numeric data received from the input, a memory for storing a number of instruction words addressable in response to said function commands, an instruction word decoder for decoding instruction words and for controlling the arithmetic unit in response thereto, first and second operational memories for storing numeric data received by said input or outputted from said arithmetic unit and a display system for displaying numeric data stored in a first one of the operational registers according to display codes stored in a second one of said operational registers, the display codes being indicative of which character positions in the display are to be blanked or to be provided with signals actuating a decimal point thereat.

Data display system for electronic calculator or microprocessor

A synchronous state counter, which is responsive to an incrementing pulse for incrementing the state of the counter, is provided with a plurality of latches which output a binary representation of the number stored in the counter. Each latch is provided with a circuit for altering a state of the latch in response to a control signal. The control signal for the latch storing the least significant bit of the number is provided by the incrementing pulse. The control signals for the latches storing bits more significant than the least significant bit of the number is provided by a plurality of circuits responsive to the incrementing pulse and to the state of each latch supplying a bit less significant than the bit stored in the particular latch being controlled.

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Garland, TX, United States of America

Larry L Miles