Digital Equipment Corporation

Other

Compaq Computer Corporation, Inc.

Larry L Biro

Matthew James Adiletta

John H Edmondson

William Ralph Wheeler

Dilip K Bhavsar

Joel J Grodstein

Nicholas L Rethman

Jeng-Wei Pan

Matthew Howard Reilly

Jengwei Pan

A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register. Compliance control circuitry, responsive to the instruction register and the TAP controller, operates to couple each BSR cell to the second input buffer when the instruction register has been loaded with a Standard defined instruction. When the instruction register has been loaded with an instruction corresponding to an input threshold voltage test of the data input pins, the compliance control circuitry couples the BSR cell to the first input buffer.

Method for cost-effective production testing of input voltage levels of

An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.

Method and apparatus for interleaving and de-interleaving YUV pixel data

In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.

Static timing verification in the presence of logically false paths

A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure is performed for each of the section designs to determine whether the section designs conform to predetermined intra-section timing constraints. A full-chip verification procedure is performed for the integrated circuit design to determine the bristle timing parameters and to determine whether the integrated circuit design conforms with predetermined intersection timing constraints.

Method for performing integrated section-level and full-chip timing

In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in a source queue and a destination queue. An execution unit successively obtains source specifiers of an instruction from the source queue, initiates an operation upon the source specifiers, reads a destination specifier from the destination queue, and retires the result at the specified destination. Read-after-write conflicts may occur because the execution unit may overlap execution of a plurality of instructions. Just prior to beginning execution of a current instruction, the destination queue is checked for conflict between the source specifiers of the current instruction and the destination specifiers of previously issued but not yet retired instructions. When an instruction is issued for execution, its destination specifiers in the destination queue are marked to indicate that they are associated with an executed but not yet retired instruction. In a preferred construction, each entry of the queue has a 'write pending' bit that is cleared during a flush and when a read pointer is incremented. An issue pointer identifies the entry of an instruction next to be issued, so that the write-pending bit is set when the issue pointer is incremented. Each entry has two comparators enabled by the write-pending bit to detect a conflict with two source specifiers.

Growing community of inventors

Oakham, MA, United States of America

Larry L Biro