Synergy Semiconductor Corporation

Larry Joseph Pollock

Atiye Bayman

George William Brown

A process for producing a small shallow-depth high-performance bipolar structure having low parasitic capacitance is disclosed wherein an active base region of a P-type material is first defined in a substrate, a portion of which is of N-type material in a device formation area surrounded by an isolating oxide regions, such as trenches or the like. An N-doped polysilicon layer is then defined over the active base region and over field oxide regions located atop the isolating trenches. This N-poly region, when treated, will provide an interdigitated collector with self aligning emitter region aligned over the active base region. After appropriate spaced isolation layers are placed, a P-poly layer is laid down and heat treated to cause the P-type doping material to diffuse into the substrate contact to the active base region. A thin buried collector layer, approximately 1.5- to 2-micron thick, can be used as a result of the combination of an interdigitated collector design and a thin epitaxial region in which the active base is located; this combination contributing to a low effective collector resistance that compensates for the increased resistance associated with a thinner buried collector layer. The process provides for collector contacts in close proximity to the active device region permitting fabrication of a small device with very low parasitic capacitance.

Process for producing a high performance bipolar structure

A sinker which is self-aligned with the oxide isolating trench which is used to define the tub in which the complete bipolar device is located. In a preferred approach to the process for forming the sinker of this invention, little additional diffusion of the sinker occurs during subsequent processing, whereby an effective sinker, aligned with the collector of the bipolar device, is achieved without additional masking steps.

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Santa Clara County, CA, United States of America

Larry Joseph Pollock