Micron Technology Incorporated

Benhov Gmbh, LLC

Other

Geogolf, LLC

Mfb Fertility, Inc.

Larry Joseph Koudele

Michael Sheperek

Bruce A Liikanen

Shane G Nowell

Mustafa Nazmi Kaynak

Kishore Kumar Muchherla

Steven Michael Kientz

Vamsi Pavan Rayaprolu

Steve Kientz

Gerald L Cadloni

Peter Sean Feeley

Guy R Wagner

Francis Chew

James Bowling French, Jr

Sampath K Ratnam

Patrick Robert Khayat

Steven Scott Williams

Christopher J Squires

Scott E Burton

John L Seabury

George Christian Cope

Douglas I McCampbell

Kenneth James Eldredge

Curtis Howard Bruner

Robert B Eisenhuth

Stephen P Van Aken

James P Crowley

Stuart A Bell

Noureddine Kermiche

Michael T Brady

Nagendra Prasad Ganesh Rao

Gary D Hamor

Zixiang Loh

Alexandra Marie Koudele

William A Marcus

Stephen P VanAken

A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

A system includes a memory device and a processing device, operatively coupled to the memory device. In some embodiments, the processing device accesses a matrix of threshold voltage offset bins, where a first dimension of the matrix is temperature and a second dimension of the matrix is a temporal voltage shift (TVS) amount. The processing device measures a temperature value based on a reference temperature value for a block family. The processing device measures a TVS value of a voltage level within one or more memory cell of the block family. The processing device retrieves, from the matrix, a threshold voltage offset bin based on the reference temperature value and the TVS value and reads data from any page of the block family via application of a threshold voltage offset, specified by the threshold voltage offset bin, to a base read level voltage.

Open block family duration limited by temperature variation

A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device initializes a block family associated with the memory device and a timer associated with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family and a hard closure of the block family in response to a first of the timer reaching a hard closure value or the block family satisfying a hard closure criteria. The processing device detects a first write amplification of a previously closed block family that employed the hard closure value and increases the hard closure value by an amount of time calculated to reduce a second write amplification, of the block family, to below a threshold write amplification.

Closing block family based on soft and hard closure criteria

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

Block family-based error avoidance for memory devices

A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

Open block family duration limited by time and temperature

A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.

Dynamic temperature compensation in a memory component

A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

Adjustment of a starting voltage corresponding to a program operation in a memory sub-system

An exemplary method of interpreting results indicated on a photographed diagnostic test comprises: sweeping the photographed diagnostic test, or cropped area of the photographed diagnostic test; creating a vector of color values including the color values obtained from a plurality of horizontal pixel positions on the photographed diagnostic test or cropped area of the photographed diagnostic test; identifying the location of the control line and each testing line depicted within the photographed diagnostic test; and calibrating to determine a hormone or analyte level corresponding to a color value of a test line. Systems of interpreting results indicated on a photographed diagnostic test are also provided.

Method for detection and interpretation of results indicated on a photographed diagnostic test

A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of memory cells of the memory device. A program targeting operation is performed on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a last programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.

A system includes a memory array; and a processing device coupled to the memory array. The processing device may be configured to iteratively adjust an active processing level, wherein, for each iteration, the processing device is configured to: determine a first set of read results corresponding to the active processing level, determine a second set of read results based on an offset processing level different than the active processing level, and incrementally adjust the active processing level based on a comparison of the first and the second read results.

Memory device with dynamic processing level calibration

A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations, including initializing a block family associated with the memory device; aggregating temperature values received from one or more temperature sensors of the memory device over time to determine an aggregate temperature; responsive to beginning to program a block residing on the memory device, associating the block with the block family; and in response to the aggregate temperature being greater than or equal to a specified threshold temperature value: performing a soft closure of the block family; initializing an extension timer; continuing to program data to the block; and performing a hard closure of the block family in response to one of the extension timer reaching an extension time value or the block family satisfying a hard closure criteria.

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

Combination scan management for block families of a memory device

A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically adjust the program-verify target according to the feedback measure.

Memory device with dynamic program-verify voltage calibration

A memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. A temperature level associated with the memory unit is determined. Based on the time after program and the temperature level, a set of read offset values to apply in executing the read operation is determined. The read operation is executed using the set of read offset values.

Selection of read offset values in a memory sub-system based on temperature and time to program levels

A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.

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Erie, CO, United States of America

Larry Joseph Koudele