Honeywell International Inc.

Larry James Miller

Pavel Zaykov

Aaron Raymond Larson

Srivatsan Varadarajan

Ryan Lawrence Roffelsen

Arthur Kirk McCready

Robert J Quirk

Richard L Frost

Paul A Fisher

Chittaranjan Kashiwar

William Ray Hancock

Pankaj Sharma

Arvind Easwaran

Jason Bialek

Murali Rangarajan

Humberto Carvalho

Andrew Wise

Michael R Wittman

Aaron R Larson

Arthur Kirk Mccready

Aaron Larson

Examples of computing systems that include I/O device(s) that respect an existing hardware resource partitioning in a modern computing platform are provided. The computing systems include at least one CPU having multiple cores and one or more CPU caches. The computing system also includes a main memory having locations, where each location maps to a set in the one or more CPU caches. A first subset of locations is partitioned for thread(s) of a first application and assigned to non-contiguous memory locations of the main memory. The computing system further includes an I/O device separate from the CPU that is configured to store I/O data in a second subset of locations that are different from the first subset of locations. The second subset of locations are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern.

Input/output device operational modes for a system with memory pools

Systems and methods for regulating memory utilization for coprocessors are provided. In one embodiment, a computing system comprises: a processor; a compute processor configured to execute one or more kernels; a memory coupled to the processor and the compute processor. The system is configured to: allocate at least one task memory transaction quota to at least a first set of tasks executed on a first core of the processor; allocate at least one compute processor memory transaction quota for executing the kernels on the compute processor; execute within a first timing window iteration the first set of tasks and the kernels, wherein the kernels are executed during the first timing window iteration until the compute memory transaction quota is depleted; and regulate a rate of memory transaction access by the one or more kernels to the memory when the first set of tasks are executing on the processor.

Systems and methods for regulating memory utilization for coprocessors

Examples of computing systems that include input/output (I/O) devices that respect an existing hardware resource partitioning in a modern computing platform are provided.

In one embodiment, a method for margin determination for a computing system with a real time operating system and priority preemptive scheduling comprises: scheduling a set of tasks to be executed in one or more partitions, wherein each is assigned a priority, wherein the tasks comprise periodic and/or aperiodic tasks; executing the set of tasks on the computing system within the scheduled periodic time window; introducing an overhead task executed for an execution duration controlled either by the real time operating system or by the overhead task; controlling the overhead task to converge on a point of failure at which a length of the execution duration of the overhead task causes either: 1) a periodic task to fail to execute within a deadline, or 2) time available for the aperiodic tasks to execute to fall below a threshold; and defining a partition margin corresponding to the point of failure.

Systems and methods for margin based diagnostic tools for priority preemptive schedulers

Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.

Systems and methods for scheduling tasks using sliding time windows

Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.

Systems and methods for simulating worst-case contention to determine worst-case execution time of applications executed on a processor

Systems and methods for displaying and controlling a remotely executed application on a display of a vehicle are disclosed. A method may include: receiving, by one or more processors, one or more video signals from one or more video sources onboard the vehicle; receiving, by the one or more processors, at a client module, a video signal including an image or display of the application executing on a remote server through a network; combining, by the one or more processors, via a video router, the received one or more video signals from the one or more video sources onboard the vehicle and the video signal including the image or display of the application executing on the remote server; and selectively displaying, by the one or more processors, on a display of the vehicle, the video signal including the image or display of the application executing on the remote server.

Systems and methods for displaying and controlling a remotely executed application on a display of a vehicle

Systems and methods for outlier mitigation in safety-critical systems are provided. In one embodiment, a computer system comprises: a processor comprising one or more processing cores; a scheduling function that schedules the execution of applications, the applications each comprise threads; a contingency budgeting manager (CBM) that defines at least a first pre-determined set of threads from the threads of the applications and assigns a contingency budget pool to the first set of threads. The first set of threads are each scheduled by the scheduling function to execute on a first processing core. The CBM is further configured to monitor execution of each of the threads of the first set of threads to identify when a first thread is an execution time outlier. When the CBM determines that the first thread is an execution time outlier, it allocates additional thread execution time from the contingency budget pool to the first thread.

System and methods for contingency budgeting for time-partitioned systems

A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.

Systems and methods for variable rate limiting of shared resource access

Systems and methods for allocation of environmentally regulated slack are provided. In one embodiment, a time-partitioned processing system comprises: at least one processing core; a memory coupled to the processing core; a real-time operating system including a scheduler configured to partition processing time for the processing core into a plurality of time periods, wherein the scheduler further budgets a pre-determined duration of processing time for executing a first budgeted time partitioned entity (TPE) by allocating at least a first allocation of time to the first budgeted TPE; wherein the scheduler utilizes at least a portion of processing time not used to execute the first budgeted TPE or any other budgeted TPE as environmentally regulated slack; wherein the scheduler allocates at least a portion of environmentally regulated slack to one or more slack consuming TPEs based on a measurement of one or more operational environment parameters associated with the processing core.

Systems and methods for allocation of environmentally regulated slack

Embodiments of the present invention provide improved systems and methods for grouping instruction entities. In one embodiment, a system comprises a processing cluster to execute software, the processing cluster comprising a plurality of processing units, wherein the processing cluster is configured to execute the software as a plurality of instruction entities. The processing cluster is further configured to execute the plurality of instruction entities in a plurality of execution groups, each execution group comprising one or more instruction entities, wherein the processing cluster executes a group of instruction entities in the one or more instruction entities in an execution group concurrently. Further, the execution groups are configured so that a plurality of schedule-before relationships are established, each schedule-before relationship being established among a respective set of instruction entities by executing the plurality of instruction entities in the plurality of execution groups.

Systems and methods for task grouping on multi-processors

Embodiments of the present invention provide improved systems and methods for processing multiple tasks. In one embodiment a method comprises: selecting a processing unit as a master processing unit from a processing cluster comprising multiple processing units, the master processing unit selected to execute master instruction entities; reading a master instruction entity from memory; scheduling the master instruction entity to execute on the master processing unit; identifying an execution group containing the master instruction entity, the execution group defining a set of related entities; when the execution group contains at least one slave instruction entity, scheduling the at least one slave instruction entity to execute on a processing unit other than the master processing unit during the execution of the master instruction entity; and terminating execution of instruction entities related by the execution group when a master instruction entity is executed that is not a member of the execution group.

Systems and methods for bounding processing times on multiple processing units

A method for scheduling schedulable entities onto an execution timeline for a processing entity in a constrained environment includes determining available capacity on the execution timeline for the processing entity based on constraints on the execution timeline over a plurality of time periods, wherein schedulable entities can only be scheduled onto the execution timeline during schedulable windows of time that are not precluded by constraints. The method further includes determining whether enough available capacity exists to schedule a schedulable entity with a budget at a rate. The method further includes when enough available capacity exists to schedule the schedulable entity with the budget at the rate, scheduling the schedulable entity onto the execution timeline for the processing entity during a schedulable window of time. The method further includes when the schedulable entity is scheduled onto the execution timeline, updating available capacity to reflect the capacity utilized by the schedulable entity.

Constrained rate monotonic analysis and scheduling

A method of ensuring high integrity of a processor is provided. The method includes executing sets of sequential instructions, each execution being based on a unique initial value, generating a computed final value responsive to each execution of a set of sequential instructions, and sending computed values to a monitoring portion of a high integrity processor monitor system responsive to the generating for each execution of the set of sequential instructions. The execution of the sets of sequential instructions tests pertinent addressing modes, operand sizes, and instruction side-effects for each instruction tested in a monitored central processing unit.

Growing community of inventors

Black Canyon City, AZ, United States of America

Larry James Miller