Texas Instruments Corporation

Larry J Mowatt

David N Walter

Robert K Peterson

Kurt Peter Wachtler

Aaron D Poteet

Larry K Johnson

Austin S O'Malley

Robert M Fife

Walter L Walas

Maurice M Guy

A high density interconnect device which creates a thin, electrically and thermally high performance package for semiconductor devices having a mechanically stable and high thermal conductivity substrate. Cavities in the substrate accommodate semiconductor devices attached directly to the substrate. The semiconductor devices include at least one optical receiver and/or transmitter. A thin film overlay having multiple layers interconnects the semiconductor devices to an array of pads on a surface of the thin film overlay facing away from the substrate. Connectors are attached to the pads to provide direct electrical and mechanical attachment to other system hardware. In one embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through holes formed through the thin film overlay. The holes may be back filled with an optical quality material.

HID land grid array packaged device having electrical and optical interconnects

A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer ( ) having a hole ( ) disposed therein for receiving an integrated circuit chip die ( ). A lower core laminate layer ( ) having a conductive layer ( ) and conductive layer ( ) disposed on opposite sides thereof is laminated to the lower surface of the layer ( ). Plated-through holes ( ), ( ) and ( ) are formed through the two layers ( ) and ( ) to connect the conductive layer ( ) with a conductive layer ( ) on the upper surface of the layer ( ). A high-density interconnect layer includes two laminate layers ( ) and ( ), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer ( ) allow for connections from the die ( ) to the conductive layer ( ). The via interconnect structures formed in the layer ( ) allow interconnection from the upper surface of layer ( ) to via interconnects formed in the layer ( ). An I/O connector is interfaced with select ones of the plated-through holes with pins ( ) and ( ). This allows an interface from the module to an operating system through pins ( ).

Multi-chip integrated circuit module

A high density interconnect land grid array package device combines various electronic packaging techniques in a unique way to create a very thin, electrically and thermally high performance package for single or multiple semiconductor devices. A thin and mechanically stable substrate or packaging material (,) is selected that also has high thermal conductivity. Cavities (,) in the substrate or packaging material (,) accommodate one or more semiconductor devices that are attached directly to the substrate or packaging material. At least one of said semiconductor devices includes at least one optical receiver and/or transmitter. A thin film overlay (,) having multiple layers interconnects the one or more semiconductor devices to an array of pads (,) on a surface of the thin film overlay facing away from the substrate or packaging material. Solder balls (,), conductive adhesive or elastomeric connectors are attached to the pads to provide direct electrical and mechanical attachment means to other system hardware. In one embodiment of the invention, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment of the invention, the optical receiver and/or transmitter receives and/or transmits light signals through holes (,) formed through the thin film overlay. The holes may be back filled with an optical quality material.

HDI land grid array packaged device having electrical and optical interconnects

A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

Multi-chip integrated circuit module and method for fabrication thereof

A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as the tooling plate during manufacture. Side-to-side interconnects are made by blind-plated vias and through-holes in the core.

Advanced polymers on metal printed wiring board

A printed wiring board is comprised of a combination of layers providing a good thermal match with surface mount components. The board consists of a core surrounded by multiple layers of dielectric and conductive materials optimized for their thermal expansion qualities. The core is also used as a heat sink for drawing excess heat from the components. An integral thermal interface region is used to dissipate the heat from the core.

Thermal interface for a printed wiring board

A circuit board system resiliently mounts a plurality of daughter boards with high circuit interconnection density on a mother board using pairs of mating connectors having welded contact members accommodated in novel arrangements in the respective connectors to permit high density of electrical interconnection with convenience and reliability. Contact parts of substantial size are welded into contacts in one connector to detachably interconnect with contact parts of similar size in mating connector to improve interconnection releability. Novel contact arrangements permit accommodation of those parts of substantial size in the mating connectors. Sheet metal spring or post parts welded into the contacts in both connectors permit the contacts to be conveniently loaded into connector bodies and permit large numbers of contact springs or posts to be soldered to terminal pads or circuit paths on mother or daughter boards with high density. Temporary fixtures mount on connectors to facilitate precise soldering of leaf springs to very closely spaced terminal pads on daughter boards; resilient mounting of the mother board facilitate daughter board engagement with heat sinks; and organizer plates fit on extending ends of connector contact posts to facilitate their insertion into mother board mounting holes with high interconnection density.

Growing community of inventors

Allen, TX, United States of America

Larry J Mowatt