Intel Corporation

Larry E Mosley

Cengiz Ahmet Palanduz

Donald S Gardner

Quat T Vu

Chunlin Liang

Chun Mu

Shawna M Liff

Qing Ma

Jian Li

Chuan Hu

Vijay K Nair

Jin Hyung Lee

Nicholas Holmberg

Clive R Hendricks

Gerhard Schrom

Edward Allyn Burton

David Gregory Figueroa

Kaladhar Radhakrishnan

Gregory F Taylor

James G Maveety

Kishore K Chakravorty

Yuegang Zhang

Edward Rudolph Prack

Dustin P Wood

Jorge Pedro Rodriguez

Xiao-Chun Mu

Bidyut K Bhattacharyya

Edward R Stanford

Huong T Do

George L Geannopoulos

Thomas J Mozdzen

Aaron Steyskal

Victor Prokofiev

Behrooz Z Mehr

Siva Natarajan

Juan P Soto

Kevin M Lenio

Xiao Chun Mu

Anna Madrid

Tony V Tran

Ken Brown

Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.

Integrated passive devices on chip

A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor.

Magnetic nanocomposite materials and passive components formed therewith

In one embodiment, an energy storage device (e.g., capacitor) may include a porous silicon layer formed within a substrate. The porous silicon layer includes pores with a mean pore diameter less than approximately 100 nanometers. A first conductive layer is formed on the porous silicon layer and a first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer to form the capacitor.

Energy storage devices formed with porous silicon

Method apparatus and material for radio frequency passives and antennas

Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization.

Magnetic microinductors for integrated circuit packaging

An apparatus includes a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits. Such capacitor may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted. The microprocessor may use a lower voltage power supply level for minimum sized fast transistors in the fast core logic portions of the microprocessor, and a more normal voltage power supply voltage level for the cache memory and I/0 transistor portions of the microprocessor. Thus a compact capacitor with multiple power and reference supply levels may be needed to provide the required power for a high frequency IC.

Split thin film capacitor for multiple voltages

A low-resistance inductor is made from a plurality of first inter-abutting insulated electrode coil sub-segments that is coupled to a plurality of second intra-abutting insulated electrode coil sub-segments that are contiguous to the plurality of first intra-abutting coil sub-segments. The first plurality and the second plurality form an helical inductor unit cell. A process of forming the low-resistance inductor includes heat curing. A system includes a low-resistance inductor and a mounting substrate.

Low resistance inductors, methods of assembling same, and systems containing same

An apparatus, and a method for forming, a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits, may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted. The microprocessor may use a lower voltage power supply level for minimum sized fast transistors in the fast core logic portions of the microprocessor, and a more normal voltage power supply voltage level for the cache memory and I/O transistor portions of the microprocessor. Thus a compact capacitor with multiple power and reference supply levels may be needed to provide the required power for a high frequency IC.

Method of forming a thin film capacitor

A low-inductance capacitor exhibits a first characteristic inductance during use in a first capacitor subsection and a second characteristic inductance during use in a second capacitor subsection, and the first and second characteristic inductances act to neutralize each other. A process of forming the low-inductance capacitor includes heat curing. A package includes a low-inductance capacitor and a mounting substrate.

Low inductance capacitors, methods of assembling same, and systems containing same

A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Controlled-resistance capacitors, and methods of assembling same

A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes.

Forming carbon nanotube capacitors

A structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Capacitor having an anodic metal oxide substrate

In one embodiment, a structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

A capacitor with reduced equivalent series resistance and reduces equivalent series inductance is provided. Capacitors are provided with multiple plate assemblies that couple to a common single first polarity terminal. Capacitors are also provided with multiple plate assemblies that each couple to a respective second polarity terminal. Fan-like plate assemblies are arranged to provide increased capacitance with reduced equivalent series resistance and reduces equivalent series inductance. Capacitors are provided that mount using surface mounting technology. Capacitors are provided that conform to existing capacitor form factors.

Capacitor device and method

Growing community of inventors

Santa Clara, CA, United States of America

Larry E Mosley