D2audio Corporation

Peavey Electronics Corporation

Intersil Americas Inc.

Other

Larry E Hand

Wilson E Taylor, Jr

Jack B Andersen

Daniel L W Chieng

Michael Allan Kost

Joel W Page

Michael Allen Kost

Douglas D Gephardt

Peter G Craven

Brian E Attwood

Richard V Spina

Daniel Chieng

Jeffrey M Klaas

Adam Zaharias

Lee Carlos Santillano

Dennis Lloyd Caldwell

Borislav Lubenov Orozov

Tonya Andersen

Thomas Richard Stuckman

Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.

Systems and methods for over-current protection

Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.

Systems and methods for controlling audio volume in the processor of a high definition audio codec

Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.

Systems and methods for controlling HDA system capabilities

Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.

Systems and methods for implementing a sample rate converter using hardware and software to maximize speed and flexibility

Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.

Systems and methods for load detection and correction in a digital amplifier

Systems and methods are provided for converting input data streams having variable input sample rates to an output sample rate, which systems and methods are used in processing the data streams. In one embodiment, a system includes a clock source, a counter configured to count cycles for a corresponding data stream, and a data processor. The data processor is configured to read the number of cycles counted by the counter between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted.

Systems and methods for sample rate conversion

Systems and methods for scaling the number of output channels that can be provided in an audio amplification system. In one embodiment, a digital pulse width modulation (PWM) amplification system includes multiple four-channel PWM controller chips that are interconnected to enable synchronization and transfer of digital audio data from one chip to another. Input audio signals received by each of the channels are processed by sample rate converters to generate internal audio signals that have a predetermined sample rate and format. Each of the channels is synchronized so that the internal audio signal of each channel can be processed and output by any of the other channels. The PWM controller chips are connected by a high-speed interconnect that enables the transfer of data between them. Each input audio signal can be mapped to any of the outputs and can be mixed with other input signals.

Systems and methods for switching and mixing signals in a multi-channel amplifier

Systems and methods for converting a data stream from a first sample rate to a second sample rate using a sample rate converter that employs selectable filters. In one embodiment, the filters are implemented by providing multiple sets of filter coefficients in a memory, selecting one of the sets of filter coefficients and performing coefficient interpolation to produce filter coefficients that are convolved with the input data stream to produce a re-sampled output data stream. The input signal can be an audio signal that is convolved with interpolated polyphase filter coefficients in the sample rate converter of a digital PWM audio amplifier. The set of filter coefficients can be selected by a value stored in a filter selection register that is modifiable by a DSP or by user input. The sets of filter coefficients can be stored in a single memory and interpolated according to a cubic spline interpolation algorithm.

SRC with multiple sets of filter coefficients in memory and a high order coefficient interpolator

Systems and methods implemented in a switching amplifier for providing consistent, matching switching between top and bottom switching devices in a switching amplifier. One embodiment includes a half-bridge circuit output stage, a driver stage and a transformer. The driver stage, which drives the switches of the output stage, is very fast, has a low propagation delay, and has minimal input capacitance. The transformer drives the drive paths from the transformer inputs to the switches. The transformer avoids resonances within the audio band and at the amplifier switching frequencies, has low and spread free leakage inductance, has enough magnetizing inductance to keep transformer currents low in proportion to the total driver stage current drain, has low core losses at the switching frequency, has minimal inductance change and operates well below its saturation point. The amplifier stage provides a substantially constant amplitude drive signal to the output power switching devices.

Switching amplifiers

A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.

Low delay corrector

Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Low-noise, low-distortion digital PWM amplifier

Systems and methods for ensuring proper phase alignment of audio signals which are processed by separate hardware channels in an audio amplification system. In one embodiment, the phase alignment is controlled by determining the number of audio data samples which are stored in the input buffers of multiple audio amplification units and controlling reads from the input buffers to minimize the difference between an actual read-write pointer differential and a target differential. In a master unit, the target differential is a predetermined target value corresponding to a desired delay in the buffer. The actual pointer differential of the master unit is passed to one or more slave units. The actual pointer differential of the master unit is used as the target differential of the slave units. The pointer differentials of the slave units are thereby driven to track the pointer differential of the master unit, keeping the units synchronized.

Phase alignment of audio output data in a multi-channel configuration

Systems and methods for detecting clipping conditions in an audio signal and processing the signal to reduce the clipping conditions. In one embodiment, a system comprises a noise shaper, a modulator, an output stage and other components. A detector detects clipping in the noise shaper and a signal processor processes the audio signal input to the noise shaper based on feedback received from the detector. The signal processor may function to modify the input audio signal in different ways in response to different conditions that are detected by the detector. A filter may be included to filter the output of the detector before being provided to the signal processor. A flag circuit may be coupled between the filter and the signal processor to assert an output signal until the signal processor resets the flag circuit.

Clip detection in PWM amplifier

Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

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Meridian, MS, United States of America

Larry E Hand