Motorola Corporation

Larry E Frisa

David L O'Meara

Michael P Woo

Stanley Michael Filipiak

Terry Grant Sparks

Yeong-Jyh Tom Lii

Craig S Lage

Andrew G Nagy

T P Ong

Mousumi Bhat

Carol M Gelatos

Philip J Tobin

Bikas Maiti

Christopher C Hobbs

Mark Hiatt

C Joseph Mogab

Iraj Eric Shahvandi

Clinton Haris

Grant McEwan

Scott S Kellogg

Michael N Montgomery

A method for removing particles from a semiconductor processing tool is provided. The method comprises providing a pick-up wafer for picking up particles from a semiconductor processing tool, inserting said pick-up wafer into said semiconductor processing tool and placing the pick-up wafer on a receiving member, applying an electrostatic charge to said pick-up wafer, leaving said pick-up wafer in said semiconductor processing tool for a predetermined dwell time; and removing said pick-up wafer from said semiconductor processing tool. Further, a method for processing semiconductor wafers is provided.

Method for removing particles from a semiconductor processing tool

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects ( and ), wherein each local interconnect ( ) cross couples the inverters of the SRAM and is formed within a single opening ( ). Also, interconnect portions ( ) of word lines are laterally offset from silicon portions ( ) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Semiconductor device, memory cell, and processes for forming them

An apparatus related to a lot signalling device used to find misplaced lots. A remote control signalling device comprises a receiver section ( ) for receiving an RF-command including a unique address of at least one of said plurality of remote control signalling devices ( ) from a central control unit ( ), an address memory ( ) for storing the address of said remote control signalling device, an output section ( ) for signalling an alarm upon receiving the RF-command, if said address included in the RF-command matches the stored address in said address memory ( ). A method for processing items at different process stages comprises the steps of: transmitting RF-commands including a unique address of at least one of said plurality of remote control signalling devices by a central control unit ( ), signalling an alarm by said remote control signalling device ( ) upon reception of an RF-command from said central control unit ( ).

Lot signalling device

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (,and,), wherein each local interconnect (,) cross couples the inverters of the SRAM and is formed within a single opening (,). Also, interconnect portions (,) of word lines are laterally offset from silicon portions (,) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region

In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.

CMOS semiconductor devices and method of formation

Growing community of inventors

Meiningen, Germany

Larry E Frisa