Micron Technology Incorporated

Semiconductor Components Industries, LLC

Other

Round Rock Research, LLC

Aptina Imaging Corporation

Micron Display Technology, Inc.

Larry Duane Kinsman

Walter L Moden

Warren M Farnworth

Jerry Michael Brooks

David J Corisis

Leonard E Mess

Salman Akram

Timothy J Allen

Alan G Wood

Terry R Lee

Derek J Gochnour

Swarnal Borthakur

Mike Brooks

Brent Keeth

Brian A Vaartstra

Jerrold L King

Marc Allen Sulfridge

Tim J Corbett

Layne G Bunker

Gary L Chadwick

Chender Huang

David A Cathey

Aaron M Schoenfeld

Eugene H Cloud

Richard W Wensel

Danny Dynka

J Mike Brooks

Manny K F Ma

Scott Donald Churchwell

Bingzhi Su

Chi-Yao Kuo

Jeff Reeder

Weng-Jin Wu

Yusheng Lin

Frank F Ross

Raymond J Beffa

Mark S Johnson

Yu-Te Hsieh

Oswald L Skeete

Ronald L Taylor

John Stuart Mullin, Sr

Mark Wolfe

Luke G England

Gregory M Chapman

Stuart L Roberts

Steven H Laney

Yu Te Hsieh

Wade D Jorgensen

Scott J Demer

Michael P Grant

Oswald Skeete

A package includes an optical sensor die, a support grid structure disposed on the optical sensor die, and an optically transparent cover attached to the support grid structure. A surface of the optical sensor die includes an optically active surface area (OASA) and an edge surface portion lying outside a perimeter of the OASA. The support grid structure disposed on the surface of the optical sensor die includes at least one pillar disposed within the OASA and an edge block disposed on the edge surface portion lying outside the perimeter of the OASA. The optically transparent cover is supported by the support grid structure at a height above the optical sensor die while maintaining an air gap between the optically transparent cover and the OASA.

Optical sensor transparent cover with array contact grid

An image sensor package may include a semiconductor wafer having a pixel array, a color filter array (CFA) formed over the pixel array, and one or more lenses formed over the CFA. A light block layer may couple over the semiconductor wafer around a perimeter of the lenses and an encapsulation layer may be coupled around the perimeter of the lenses and over the light block layer. The light block layer may form an opening providing access to the lenses. A mold compound layer may be coupled over the encapsulation layer and the light block layer. A temporary protection layer may be used to protect the one or more lenses from contamination during application of the mold compound and/or during processes occurring outside of a cleanroom environment.

Image sensor packages formed using temporary protection layers and related methods

An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

Image sensor semiconductor packages and related methods

Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.

Chip scale package and related methods

Various embodiments of the present technology may comprise a method and apparatus for an image sensor with a thermal equalizer for distributing heat. The method and apparatus may comprise a thermal equalizer disposed between a sensor die and a circuit die to prevent uneven heating of the pixels in the sensor die. The method and apparatus may comprise a thermal equalizer integrated within the circuit die.

Methods and apparatus for a thermal equalizer in an image sensor

An image sensor may include an infrared radiation-blocking layer. The infrared radiation-blocking layer may block infrared radiation from reflecting off of metal layers formed beneath pixel structures in the image sensor so that the reflected light does not reach the photodiodes. The infrared radiation-blocking layer may be formed between a backside redistribution layer and an epitaxial silicon layer in which pixel structures such as photodiodes and transistors are formed. The infrared radiation-blocking layer may be formed from a pre-existing metal layer between the backside redistribution layer and the epitaxial silicon layer. The infrared radiation-blocking layer may prevent the image sensor from generating inadvertent photocurrents in response to reflected infrared light.

Image sensors with infrared-blocking layers

A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.

Multi-chip package for imaging systems

Disclosed herein is a stacked chip package including an image sensor including a recess formed on a surface thereof, and a digital signal processor chip that is positioned within the recess. Also disclosed herein is a method of fabricating a stacked chip package including the steps of forming a recess on a surface of an image sensor and positioning a digital signal processor in the recess of the image sensor.

Stacked sensor packaging structure and method

Electronic device packages comprise transparent substrates covering an active surface of an optically interactive electronic device. In some embodiments, the optically interactive electronic device is bonded to conductive traces formed directly on the transparent substrate. In other embodiments, a secondary substrate comprising a plurality of conductive traces is disposed between the transparent substrate and the optically interactive electronic device.

Electronic device package with an optical device

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

256 Meg dynamic random access memory

Growing community of inventors

Boise, ID, United States of America

Larry Duane Kinsman