Advanced Micro Devices Corporation

Ati Technologies Ulc

Globalfoundries Inc.

Legerity, Inc.

Advanced Micro Systems, Inc.

Larry David Hewitt

Dale E Gulick

Paul C Miranda

Brian C Barnes

Andy Lambrecht

Mike Webb

David E Norris

David N Suggs

Indrani Paul

Derrick R Meyer

Kevin Michael Lepak

Scott E Swanstrom

Sriram Sambamurthy

Aaron Joseph Grenat

Dana Glenn Lewis

Wonje Choi

James B Keller

Geoffrey S Strongin

William Alexander Hughes

Frank P Helms

Michael Hogan

Samuel D Naffziger

Carlin D Cabler

Glen W Brown

Steven Frederick Liepe

Leonardo De Paula Rosa Piga

Jeffrey M Blumenthal

Ryan E Feemster

Martin P Soques

Adam Neil Calder Clark

Sandhya Shyamasundar

Scott A White

Gerald Robert Talbot

Paul G Schnizlein

Jonathan Mercer Owen

Alfredo R Linz

Anil Harwani

Michael J Tresidder

Stephen C Ennis

Geoffrey E Brehmer

Karthik Rao

Leonardo Piga

James O Mergard

Michael E Spak

Yanfeng Wang

Paul Mackey

Noah Beck

Sriram Sundaram

David J Guercio

Greg Smaus

Huining Liu

Alan T Torok

James Bunnell

Mark Douglas Hummel

Stephen Victor Kosonocky

Frederick Daniel Weber

Emerson S Fang

Alfred C Hartmann

R Stephen Polzin

John P Petry

Richard Martin Born

Daniel L Bouvier

Tahsin Askar

Thomas James Gibney

Erik D Swanson

Frank Barth

Shwetal Arvind Patel

Richard W Reeves

Geoffrey S S Strongin

Michael L Golden

Ross Voigt La Fetra

Joerg Winkler

Rohit Kumar

Eric G Chambers

Michael Bienek

Adam N C Clark

Thomas Burd

Gokul Subramani Ramalingam Lakshmi Devi

John Vincent Faricelli

Ross Voigt LaFetra

Veechoong “Jonas” Chia

Xiuting Kaleen Cheng Man

Dele E Gulick

Methods and systems for facilitating improved power consumption control of a plurality of processing cores are disclosed. The methods improve the power consumption control by performing power throttling based on a determined excess power consumption. The methods include the steps of: monitoring using at least one event count component in the respective processing core a plurality of distributed events; calculating an accumulated weighted sum of the distributed events from the event count component; determining an excess power consumption by comparing the accumulated weighted sum with a threshold power value; and adjusting power consumption of the respective processing core based on the determined excess power consumption.

System and method for controlling power consumption in processor using interconnected event counters and weighted sum accumulators

A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

Operating voltage adjustment for aging circuits

Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Platform power manager for rack level power and thermal constraints

A method and apparatus for scrambling and descrambling data in a computer system includes transmitting non-scrambled data from a first high speed inter chip (IP) link circuit located on a first chip to a first serializer/deserializer (SERDES) physical (PHY) circuit located on the first chip, the first high speed link IP indicating the data is not scrambled. The received non-scrambled data is scrambled by the first SERDES PHY circuit and transmitted to a second chip. The received scrambled data is descrambled by a second SERDES PHY circuit located on the second chip. The non-scrambled data is transmitted by the second SERDES PHY circuit to a second high speed link IP circuit located on the second chip to a third circuit for further processing or transmission.

Method and apparatus for data scrambling

Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.

Electrical design current throttling

The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.

Voltage regulators for an integrated circuit chip

A system and method for managing operating modes within a semiconductor chip for optimal power and performance while meeting a reliability target are described. A semiconductor chip includes a functional unit and a corresponding reliability monitor. The functional unit provides actual usage values to the reliability monitor. The reliability monitor determines expected usage values based on a reliability target and the age of the semiconductor chip. The reliability monitor compares the actual usage values and the expected usage values. The result of this comparison is used to increase or decrease current operational parameters.

Dynamic reliability quality monitoring

An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

Buffering non-posted read commands and responses

An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equalizer of the data communications link with predetermined equalizer settings selected from a plurality of predetermined equalizer settings based on a selected rate of data communications for the link.

In-band method to configure equalization levels

A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.

Technique for negotiating a width of a packet-based communication link

A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

In-band power management in a communication link

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Austin, TX, United States of America

Larry David Hewitt