Cirrus Logic Inc.

Broadcom Corporation

Lake Cherokee Hard Drive Technologies, LLC

Larry D King

Trent O Dudley

Neal Glover

Richard T Behrens

Alan J Armstrong

Kent D Anderson

Bill R Foland

Paul M Romano

Petro Estakhri

Son H Ho

Phuc Tran

Maryam Imam

Mike Machado

German S Feyh

John S Geldman

Louis Supino

Bhupendra K Ahuja

Roger McPherson

Palaksha Setty

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

Synchronous read channel

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

Synchronous read channel employing a digital center frequency setting

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.

Synchronous read channel integrated circuit employing a channel quality

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a partial response of the form (1-D)(1+D).sup.n where n&gt;1, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector.

Synchronous read channel integrated circuit employing discrete time

In an optical disk storage device, a differential phase detector is disclosed for generating a position error signal independent of the frequency content of the recorded data. A pair if diagonal signals S1 and S2 are generated by adding a pair of respective quadrants of a four-quadrant photodetector, where the phase offset between the diagonal signals represents the position error of the pit image as it passes over the photodetector. The position error is determined in the present invention by computing the difference between a positive and negative correlation of the diagonal signals S1 and S2, otherwise referred to as a dual arm correlation (DAC) ##EQU1## where .DELTA. is the correlation offset and L is the correlation length. In the preferred embodiment, the correlation offset .DELTA. is adaptively adjusted to maximize the correlation between S1 and S2. In this manner, the position error estimate is substantially insensitive to the frequency content of the recorded data. Furthermore, this method extends the position error over a range of plus or minus one-half a track, which facilitates generating a quadrature signal for use in counting track crossings during seek operations.

Differential phase error detector using dual arm correlation for servo

A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.

Synchronous read channel employing a sequence detector with programmable

Synchronous read channel employing discrete timing recovery, transition

An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.

Integrated circuit servo system control for computer mass storage device

A burst magnitude comparator and an instruction sequencer are employed in a servo system controller to rapidly determine position correction information for moving a transducer head over the center line of a track recorded on a disk in a mass storage disk drive. The burst magnitude comparator selects at least two burst signals derived from bursts recorded at predetermined locations relative to the center line from which to derive a correction control signal, based on a predetermined relationship of the burst signals, and supplies the selected burst signals in a predetermined order to facilitate calculation of the correction signal by a data processor used with the servo system controller. An instruction sequencer controls a sequence of converting the analog burst signals from the head to digital burst signals without intervention or control from the data processor. By ordering the signals with the burst magnitude comparator and by sequencing the conversion of the signals, the calculation is speeded and the processing and code requirements for the data processor are greatly reduced, thereby reducing transport delay and freeing the resources of the processor for use in other, potentially more important tasks associated with the servo controller.

Burst comparison and sequential technique for determining servo control

A servo system controller for a disk drive device which includes a rotating mass storage disk incorporates a timing error determining circuit for determining rotational speed variations in the disk from information contained in a servo field recorded in a track. A timing error signal is supplied when the speed variation exceeds a threshold, thus indicating an unacceptable level of speed variation. A digital synchronizer responds to asynchronous servo data signals from the disk to establish a cell clock signal occurring about a normal frequency, a cell during which only one servo data signal will occur, and a cell data signal which occurs during the cell. The cell clock signal clocks logical operations on a synchronous basis, and servo data signals are reliably captured. A concurrence determining circuit determines the degree of concurrence between the predetermined series of cell data signals and an actual pattern of signals derived from the servo field, and recognizes the servo control information from less than complete concurrence of the derived pattern and the actual expected pattern. Normal operation is permitted even through slight inconsistences may be detected, improving data throughput while still achieving an adequate level of error tolerance.

Sequence, timing and synchronization technique for servo system

Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors 'on the fly' i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial. Cyclic redundancy check (CRC) information is adjusted as introduced errors are identified during the Chien search, thus reducing the time required to protect against ECC miscorrection. Externally-specified error thresholds allow detection of excessive numbers of errors.

Fast and efficient circuit for identifying errors introduced in

Described in detail herein are the detection and windowing capabilities of the present invention which are critical for reading correct data in normal operations and recovering data during error conditions. Also described herein are the various programmable features of the detection windows of the invention. The flexibility of these features allows the designer to optimize the optical controller for the unique requirements of the particular optical drive and medium in use.

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Boulder, CO, United States of America

Larry D King