Integrated Device Technology, Inc.

Mips Computer Systems, Inc.

Larry D Johnson

David J Pilling

Mark G Johnson

A redundancy circuit for a semiconductor memory device utilizes a fuse ladder comprising alternating programmable resistive fuses and signal restorers connected to one another in series. The signal restorers coupled between the fuses prevent the formation of a high impedance resistive line with a floating node when one of the fuses in the ladder is blown.

Adjacent row shift redundancy circuit having signal restorer coupled to

A fused decoder for selecting one or more elements of an array, such as a row of memory, is provided. The corresponding row of memory can be permanently deselected by blowing the fuse of the decoder. Array components such as a redundant row of memory, can be substituted for the deselected component. The decoder includes a gate formed exclusively from NMOS transistors so that the decoder can provide a select signal in response to an address without an PMOS transistor responding to the address- By eliminating PMOS transistors from the gate portion of the decoder, the load presented to the address lines is reduced.

Redundancy selection apparatus and method for an array

A redundant array element or signal line is selectively added and an defective array element or signal line is eliminated by the method and apparatus of the present invention. A multiplexor receives an input signal and a neighboring input signal and outputs one of these two input signals in response to a control signal. A fuse is provided in connection with each output line and configured such that if the fuse is unblown, the device selects the same input as was selected by its upstream neighbor. If a fuse if blown, the multiplexor will select the second input and will output a control signal to its downstream neighbor causing the downstream neighbor to also output its second input line and to output a control signal to its downstream neighbor to select the second input line. The substitution of a redundant element or line is achieved by blowing a single fuse and the circuitry adds only a single mux delay to the critical path.

Redundant element substitution apparatus

A sense amp and latch for sensing and latching data on a plurality of bit and inverse bit lines is provided. A sense amp power line which connects the sense amp to a ground line also decouples the bit lines from the sense amp during the evaluation process. The circuit allows for automatic latching of the data which the sense amp evaluated without requiring the generation of other timing signals. Capacitive loading on each of the two sides of the sense amp are equal.

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Larry D Johnson