Storage Technology Partners

Storage Technology Partners (through Stc Computer Research Corporation)

Larry Cooke

John J Zasio

Raymond Paul

An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the 'master' and the second latch element operates as the 'slave' of a master/slave latch circuit. When operating as a shift register circuit, shift-in data is coupled to the second latch element, and this second latch element operates as the 'master' and the third latch element operates as the 'slave' of a master/slave latch through which data is selectively shifted by appropriate clock signals.

System for detecting and correcting errors in a CMOS computer system

CMOS scannable latch

A method and apparatus for reducing the number of areas multiply exposed when a workpiece is scanned by an electron beam or other exposing radiation. The areas to be exposed are described as a plurality of rectangular shapes. The method of the invention sorts the data describing the rectangles. Rectangles which overlap or abut in one direction and are coextensive in another are merged such that a smaller number of rectangles is formed. This smaller number describes an area substantially equivalent to the original pattern. The smaller number of rectangles resulting from the merging method will have a minimum of disadvantageously overlapping or abutting rectangles.

Electron beam exposure system

A system and method for calibrating scanning beam systems, such as electron beam systems, so that a plurality of such systems are compatible one with another, thereby allowing an object that is scanned on one system to be transferred to another system while still maintaining proper alignment between the pattern(s) scanned on the object by one system and the pattern(s) scanned on the object by another system. A calibration plate, having an array of calibration marks thereon at prescribed locations, is made on a first system. This plate is then transferred to a second system where the location of the calibration marks is measured. The measured locations are fitted mathematically to the prescribed locations in order to minimize error. Nonetheless, some error will be present due to the slight misalignments and nonlinearities, such as mirror distortion, that are present between any two scanning beam systems. This error is determined by comparing the fitted measured locations to the prescribed locations. An error map is created that characterizes this error by location, for the particular scanning beam system being calibrated. The information contained in this error map is used to subsequently compensate the movement of the calibrated system, using interpolation when necessary, so that the movements of the calibrated system accurately track, and hence are aligned with, the movements of the first system. Internal compensation may also be performed on each system to account for known errors and nonlinearities associated with the operation of the individual system.

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Cupertino, CA, United States of America

Larry Cooke