Texas Instruments Corporation

Lockheed Martin Corporation

Qorvo Us, Inc.

Triquint Semiconductor Corporation

Larry Charles Witkowski

Kevin L Robinson

Ming-Yih Kao

Pertti K Ikalainen

Hua Q Tserng

Andrew Arthur Ketterson

Oren B Kesler

Dana Jay Sturzebecher

Charles M Rhoads

Oleh Krutko

Arthur Donald Ballato

Robert C Voges

A BAW device includes a substrate, a first reflector, and at least two BAW transducers. The first reflector resides over the substrate and has a plurality of reflector layers. A first BAW transducer resides over a first section of the first reflector, has a first series resonance frequency, and has a first piezoelectric layer of a first thickness between a first top electrode and a first bottom electrode. The second BAW transducer resides over a second section of the first reflector, has a second series resonance frequency that is different than the first series resonance frequency, and has a second piezoelectric layer of a second thickness, which is different than the first thickness, between a second top electrode and a second bottom electrode.

BAW structure having multiple BAW transducers over a common reflector, which has reflector layers of varying thicknesses

Embodiments include but are not limited to apparatuses and systems including an integrated capacitor. An integrated capacitor may include a substrate, a first capacitor plate having four edges, and a second capacitor plate overhanging the four edges of the first capacitor plate and disposed over the first capacitor plate such that the first capacitor plate is disposed between the second capacitor plate and the substrate.

Integrated capacitor having an overhanging top capacitor plate

A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Method for fabrication of devices in a multi-layer structure

A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same

In one form of the invention, a field effect transistor is disclosed, the transistor comprising: a channel between a source and a drain, the channel comprising: a first region 22 of a first semiconductor material having a first doping concentration; a second region 20 of a second semiconductor material having a second doping concentration, the second region 20 lying above the first region 22; a third region 18 of the first semiconductor material having a third doping concentration, the third region lying above the second region 20, wherein the first doping concentration is higher than the second and third doping concentrations; and a gate electrode 12 lying above the third region 18, whereby an electrical current flows in the channel primarily in the first region 22 or primarily in the second region 20 by varying a voltage on the gate electrode 12.

Method for forming a linear field effect transistor

Linear field effect transistor

A GaAs monolithic waveguide switch and system for low power consumption and high frequency switching wherein a single GaAs chip is flip-chip mounted onto a waveguide slot and inserted between interconnecting waveguides to provide single pole single throw switching. The GaAs chip includes an array of MESFETs along with connecting electrodes configured to provide low loss in the biased state and high loss in the unbiased state. The use of a single GaAs monolithic chip provides improved RF performance and manufacturability over discrete devices and provides lower power consumption as compared with silicon PIN diode waveguide switches.

Growing community of inventors

Plano, TX, United States of America

Larry Charles Witkowski