International Business Machines Corporation

Larry C Martin

John Bula

Claude Louis Bertin

Robert Daniel Love

Thomas A Williams

Leo A Gladstein

An FET substrate voltage generator circuit is disclosed for converting a single power supply and ground potential to a negative potential having an absolute value whose magnitude is greater than the power supply potential and applying that potential to the substrate of an integrated circuit upon which it is formed. The circuit dissipates less power per unit of current supplied by the circuit and occupies less space than do prior art circuits. The circuit applies the principle of voltage doubling to a first capacitor to achieve the desired voltage magnitude across a second capacitor and then applies the principle of a.c. coupling to that second capacitor connected through an impedance to the first capacitor, to achieve the desired polarity inversion for the substrate voltage to be generated. This circuit provides the current generating capacity necessary to drive the substrate to a negative voltage and sink the required current so as to maintain the substrate at an adequate negative bias.

Substrate generator

Use of a residual charge bleed-off diode connected to the gate of an FET device in a Read Only Storage (ROS) is disclosed. The ROS is personalized by cutting selected gate leads in an array of FETs with a laser beam. Experience has shown that static electric charges on the lead due to handling prior to cutting become isolated at the gate after the gate lead is cut, producing an unpredictable conduction state for the FET instead of a solid off-state as desired. By providing a bleed-off diode which remains connected to the FET gate after the cut is made, the charges are allowed to leak away from those FETs whose gates have been cut while, at the same time, preventing the voltage of the FET gate from floating. The diode is oriented so as to offer a high impedance to current flowing from the gate node when the gate is biased for FET conduction. This minimizes the effect of the diode on circuit speed when the gate remains connected with the balance of the read only storage circuitry. If the gate and diode have been selectively severed from the balance of the read only storage circuitry, in the course of programming the storage, any residual charge on the gate is conducted through the diode by virtue of its reverse bias leakage or forward biased conduction state, depending upon the polarity of the residual charge on the gate.

Laser cut storage cell

A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. A pair of enhancement mode/depletion mode inverters connected in cascade configuration serves to generate the true and complement output signals which are isolated from noise at the input line by a symmetric pair of clocked FETs.

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Tucson, AZ, United States of America

Larry C Martin