Ericsson Gmbh

Telefonaktiebolaget Lm Ericsson (publ)

Infineon Technologies Ag

Infineon Technologies North America Corp.

Ericcson Inc.

Larry C Leighton

Thomas W Moller

Bengt Ahl

Ted Johansson

Prasanth Perugupalli

Henrik Hoyer

Nagaraj V Dixit

Tom Moller

Gordon Ma

Ivar Hamberg

Gordon C Ma

Jan Johansson

Bertil Skoglund

Nils Af Ekenstam

Nagaraj Vishwanath Dixit

A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Bond wire tuning of RF power transistors and amplifiers

A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate, thereby reducing resistance and inductance in the ground signal path and increasing the efficiency of the power package.

Multiple ground signal path LDMOS power package

Conventional broadband RF power amplifiers use a &frac14; wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second &frac14; wavelength transmission line to decouple the drain bias DC source from the drain circuitry, taking up considerable printed circuit board space. A novel broadband RF power amplifier uses a transistor with separate terminals for injection of gate bias and drain bias DC sources, eliminating the need for &frac14; wavelength transmission lines, thereby freeing up space and allowing higher density packaging. The power amplifier transistor can be implemented with a single die circuit or multiple die circuits operating in parallel.

RF power transistor with internal bias feed

A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal. A plurality of corresponding output matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple the respective component output signals at the transistor outputs to an output impedance.

Multi-stage, high frequency, high power signal amplifier

A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage elements to obtain improved stability and operational performance.

Stability enhanced multistage power amplifier

Gain and bandwidth enhancement of a RF power amplifier package is effected by electrically coupling a power transistor to a RF signal source with an inductance, and further electrically coupling the input and common element terminals of the power transistor with a shunt inductance. The shunt inductance is chosen such that its reactance is the conjugate of the reactance of the power transistor's common-input capacitance. A similar conjugate matching output circuit is provided to electrically couple the transistor's output and common element terminals to a load. The shunt inductors are implemented on the package substrate by connecting the respective input and output transistor terminals to grounded shunt caps via bond wires.

Gain and bandwidth enhancement for RF power amplifier package

A push-pull transistor chip comprises a single/semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.

Single chip push-pull power transistor device

A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

Functional lid for RF power package

The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing, the bipolar power transistor. The power transistor comprises a substrates, a collector layer of a first conductivity type on the substrate, a base of a second conductivity type electrically connected to the collector layer, an emitter of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer, the interconnecting layers being at least in parts separated from the collector layer by an insulation oxide. According to the invention the power transistor substantially comprises a field shield electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Vertical bipolar transistor having a field shield between the metallic interconnecting layer and the insulation oxide

An electrical assembly includes an IC package having a thermally conductive mounting flange in contact with a heat sink. A thermally conductive casing is secured to the heat sink, the casing at least partially enclosing the IC package. A resilient retaining member is disposed between the casing and IC package, the retaining member applying sufficient force on the IC package so as to maintain good thermal contact between the mounting flange and heat sink.

Thermally conductive mounting arrangement for securing an integrated circuit package to a heat sink

A thermally conductive mounting flange of an IC package is placed directly on a heat sink surface between respective sections of single layer PC board attached to the heat sink, such that electrical leads extending from opposing sides of the package are positioned over corresponding conductive areas formed on the surface of the respective adjacent PC board section. The leads are electrically coupled with the conductive areas by respective tie-down screws fastened through dielectric isolating washers. The screws are tightened sufficiently against the isolating washers so as to press the respective package leads into solid electrical contact with the conductive areas. Portions of the respective leads and conductive areas surrounding the tie-down screws are cut-away to prevent electrical contact, in order to avoid shorting the leads and/or conductive areas to the heat sink via the tie-down screws. Alternately, respective ends of a retaining spring used to secure the IC package to the heat sink mounting flange are also secured by the package lead tie-down screws, such that the screws both secure the package against the heat sink and press the package leads into solid electrical contact with the respective conductive areas.

Capacitive mounting arrangement for securing an integrated circuit

The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing the bipolar power transistor. The power transistor comprises a substrate (13), a collector layer (15) of a first conductivity type on the substrate, a base (19) of a second conductivity type electrically connected to the collector layer, an emitter (21) of the first conductivity type electrically connected to the base, the base and the emitter each being electrically connected to a metallic interconnecting layer (31,33), the interconnecting layers (31,33) being at least in parts separated from the collector layer (15) by an insulation oxide (17). According to the invention the power transistor substantially comprises a field shield (25) electrically connected to the emitter, and located between the metallic interconnecting layer of the base and the insulation oxide.

Method for manufacturing vertical bipolar transistor having a field

A plurality of transistor cells (36) formed on a semiconductor substrate (32) are connected to form a radio frequency power transistor device (30), whereby individual conductive paths (38) are formed on one side of the substrate (32) to connect respective common gate terminals (34) of adjacent transistor cells (36) in series. A further conductive path (40) is formed on an opposite side of the substrate connecting respective drain terminals (35) of the transistor cells (36) in parallel. A resistive element (42) is interposed in the conductive path (38) connecting each adjacent pair of gate terminals (34). The conductivity of the respective resistive elements (42) is selected so as to adequately provide a conductive pathway for connecting the respective gate terminal outputs, while being sufficiently resistive such that each gate terminal 34 'sees' an electrical circuit termination.

Resistive interconnect of transistor cells

A thermally conductive mounting flange of an IC package is placed directly on a heat sink surface between respective sections of single layer PC board attached to the heat sink, such that electrical leads extending from opposing sides of the package are positioned over corresponding conductive areas formed on the surface of the respective adjacent PC board section. The respective package leads are each connected to the corresponding PC board areas by one or more flexible bond wires. In addition to electrically connecting the package leads to the respective PC board sections, the bond wires collectively secure the package to the heat sink in a manner allowing for relative lateral movement between the respective flange and heat sink surfaces in response to thermal stresses.

Growing community of inventors

Scottsdale, AZ, United States of America

Larry C Leighton